MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1572

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Functional Description
A direct consequence of the first requirement is that the minimum number of time quanta
per CAN bit must be 8, so the oscillator clock frequency should be at least eight times the
CAN bit rate. The minimum frequency ratio specified in
choosing a high enough peripheral clock frequency when compared to the oscillator clock
frequency, or by adjusting one or more of the bit timing parameters (PRESDIV, PROPSEG,
PSEG1, PSEG2). As an example, taking the case of 64 MBs, if the oscillator and peripheral
clock frequencies are equal and the CAN bit timing is programmed to have 8 time quanta
per bit, then the prescaler factor (PRESDIV + 1) should be at least 2. For prescaler factor
equal to one and CAN bit timing with 8 time quanta per bit, the ratio between peripheral
and oscillator clock frequencies should be at least 2.
25.4.11.1 Freeze Mode
This mode is entered by asserting the HALT bit in the MCR Register or when the i.MX28
is put into Debug Mode. In both cases, it is also necessary that the FRZ bit is asserted in
the MCR Register and the module is not in any of the low power modes (Disable, Stop).
When Freeze Mode is requested during transmission or reception, FlexCAN does the
following:
After requesting Freeze Mode, the user must wait for the FRZ_ACK bit to be asserted in
MCR before executing any other action, otherwise FlexCAN may operate in an unpredictable
way. In Freeze mode, all memory mapped registers are accessible.
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• Waits to be in either Intermission, Passive Error, Bus Off or Idle state
• Waits for all internal activities like arbitration, matching, move-in and move-out to
• Ignores the Rx input pin and drives the Tx pin as recessive
• Stops the prescaler, therefore halting all CAN protocol activities
• Grants write access to the Error Counters Register, which is read-only in other modes
• Sets the NOT_RDY and FRZ_ACK bits in MCR
Table 25-8. Minimum Ratio Between Peripheral Clock Frequency and CAN Bit Rate
finish
Number of Message Buffers
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
16
32
64
Table 25-8
Minimum Ratio
16
8
8
can be achieved by
Freescale Semiconductor, Inc.