MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 344

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

AHB-to-APBH Bridge Overview
The DMA controller uses the APBH bus to transfer read and write data to and from each
peripheral. There is no separate DMA bus for these devices. Contention between the DMA's
use of the APBH bus and the AHB-to-APB bridge functions' use of the APBH is mediated
by an internal arbitration logic. For contention between these two units, the DMA is favored
and the AHB slave will report "not ready" through its HREADY output until the bridge
transfer can complete. The arbiter tracks repeated lockouts and inverts the priority,
guaranteeing the CPU every fourth transfer on the APB.
344
Figure 6-1. AHB-to-APBH Bridge DMA Block Diagram
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HSADC
LCDIF
SSP0
SSP1
SSP2
SSP3
AHB Slave
APBH Master
AHB
AHB-to-APBH Bridge
AHB-to-APBH DMA
ATA_NAND0
ATA_NAND1
ATA_NAND2
ATA_NAND3
ATA_NAND0
ATA_NAND1
ATA_NAND2
ATA_NAND3
AHB Master
Freescale Semiconductor, Inc.