MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1579

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
SOFT_RST
WAK_MSK
WAK_SRC
NOT_RDY
FRZ_ACK
SLF_WAK
LPM_ACK
WRN_EN
SRX_DIS
RSVD3
SUPV
HALT
Field
BCC
FEN
FRZ
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0 Enable the FlexCAN module
The FRZ bit specifies the CAN behavior when the HALT bit in the MCR Register is set or when Debug Mode
is requested at MCU level (through assertion of the ipg_debug signal on the IP Interface). When FRZ is
asserted, CAN is enabled to enter Freeze Mode. Negation of this bit field causes CAN to exit from Freeze
Mode.
This bit controls whether the FIFO feature is enabled or not. When FEN is set, MBs 0 to 7 cannot be used
for normal reception and transmission because the corresponding memory region ($80-$FF) is used by the
FIFO engine.
Assertion of this bit puts the CAN module into Freeze Mode. The ARM should clear it after initializing the
Message Buffers and Control Register. No reception or transmission is performed by CAN before this bit is
cleared. While in Freeze Mode, the ARM has write access to the Error Counter Register, that is otherwise
read-only. Freeze Mode can not be entered while CAN is in any of the low power modes.
This read-only bit indicates that CAN is either in DisableMode, StopMode or Freeze Mode. It is negated
once CAN has exited these modes.
This bit enables the Wake Up Interrupt generation.
When this bit is asserted, CAN resets its internal state machines and some of the memory mapped registers.
The following registers are reset: MCR (except the MDIS bit), TIMER, TCR, ECR, ESR, IMASK1, IMASK2,
IFLAG1, IFLAG2. Configuration registers that control the interface to the CAN bus are not affected by soft
reset.
This read-only bit indicates that CAN is in Freeze Mode and its prescaler is stopped.
This bit configures some of the CAN registers to be either in Supervisor or Unrestricted memory space.
This bit enables the Self Wake Up feature when CAN is in Stop Mode. If this bit had been asserted by the
time CAN entered StopMode, then CAN will look for a recessive to dominant transition on the bus during
these modes.
When asserted, this bit enables the generation of the TWRN_INT and RWRN_INT flags in the Error and
Status Register. If WRN_EN is negated, the TWRN_INT and RWRN_INT flags will always be zero,
independent of the values of the error counters, and no warning interrupt will ever be generated.
This read-only bit indicates that CAN is either in Disable Mode or Stop Mode.
This bit defines whether the integrated low-pass filter is applied to protect the Rx CAN input from spurious
wake up.
This bit field is reserved.
This bit defines whether CAN is allowed to receive frames transmitted by itself.
This bit is provided to support Backwards Compatibility with previous CAN versions.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_CAN_MCR field descriptions (continued)
Description
Chapter 25 Controller Area Network (FlexCAN)
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