MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2098

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
33.4.13 Digital Video Interface Control0 Register (HW_LCDIF_DVICTRL0)
The Digital Video interface Control0 register provides the overall control of the Digital
Video interface.
This register gives information about the horizontal active, horizontal blanking and total
number of lines in the ITU-R BT.656 interface.
EXAMPLE
Address:
Re-
33.4.14 Digital Video Interface Control1 Register (HW_LCDIF_DVICTRL1)
The Digital Video interface Control1 register provides the overall control of the Digital
Video interface.
This register contains information about the Field1 start and end, and the Field2 start in the
ITU-R BT.656 interface.
2098
set
Bit
W
H_ACTIVE_CNT
R
H_BLANKING_
31
RSRVD1
RSRVD0
0
31 28
27 16
15 12
RSRVD1
Field
11 0
CNT
30
0
//525/60 video system
HW_LCDIF_DVICTRL0_H_ACTIVE_CNT_WR(0x5A0);//1440
HW_LCDIF_DVICTRL0_H_BLANKING_CNT_WR(0x106);//262
//625/50 video system
HW_LCDIF_DVICTRL0_H_ACTIVE_CNT_WR(0x5A0);//1440
HW_LCDIF_DVICTRL0_H_BLANKING_CNT_WR(0x112);//274
29
0
HW_LCDIF_DVICTRL0
28
0
Reserved bits, write as 0.
Number of active video samples to be transmitted. (Mostly will be 1440 for both PAL and NTSC). Must
always be a multiple of 4.
Reserved bits, write as 0.
Number of blanking samples to be inserted between EAV and SAV during horizontal blanking interval.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
H_ACTIVE_CNT
HW_LCDIF_DVICTRL0 field descriptions
23
0
22
0
8003_0000h base + C0h offset = 8003_00C0h
21
0
20
0
19
0
18
0
17
0
16
0
15
0
Description
RSRVD0
14
0
13
0
12
0
11
0
10
0
0
9
0
8
H_BLANKING_CNT
Freescale Semiconductor, Inc.
0
7
0
6
0
5
0
4
3
0
0
2
0
1
0
0