MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1223

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

14.8.164 DRAM Control Register 175 (HW_DRAM_CTL175)
This is a DRAM configuration register.
Address:
Re-
Freescale Semiconductor, Inc.
set
Bit
W
R2R_SAMECS_
W2W_DIFFCS_
R
R2R_DIFFCS_
PRIORITY
PRIORITY
AXI5_W_
31
AXI5_R_
0
RSVD4
RSVD3
RSVD2
RSVD1
RSVD4
31 27
26 24
23 19
18 16
15 11
31 27
26 24
Field
10 8
Field
DLY
DLY
DLY
7 3
2 0
30
0
RSVD4
29
0
HW_DRAM_CTL175
28
0
Always write zeroes to this field.
Additional delay to insert between reads and reads to the same chip select.
Defines the number of additional clocks of delay to insert between two read commands to the same chip
select.
Always write zeroes to this field.
Additional delay to insert between reads and reads to different chip selects.
Defines the number of additional clocks of delay to insert from a read command to one chip select to a read
command to a different chip select.
Always write zeroes to this field.
Priority of write cmds from AXI port 5.
Always write zeroes to this field.
Priority of read cmds from AXI port 5.
Always write zeroes to this field.
Additional delay to insert between writes and writes to different chip selects.
Defines the number of additional clocks of delay to insert from a write command to one chip select to a write
command to a different chip select.
27
0
26
DIFFCS_
0
W2W_
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
DLY
25
0
24
0
23
0
HW_DRAM_CTL174 field descriptions
HW_DRAM_CTL175 field descriptions
800E_0000h base + 2BCh offset = 800E_02BCh
22
0
RSVD3
21
0
20
0
19
0
18
TBST_INT_
0
INTERVAL
17
0
16
0
15
0
Description
Description
14
0
RSVD2
13
0
12
0
Chapter 14 External Memory Interface (EMI)
11
0
10
SAMECS_
0
R2W_
DLY
0
9
0
8
0
7
0
6
RSVD1
0
5
0
4
3
0
DIFFCS_
0
2
R2W_
DLY
0
1
1223
0
0