MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2207

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

The DIGCTL module contains the HW_DIGCTL_CTRL_SAIF_CLKMUX_SEL bit field
which selects the clock sources for the SAIFs input BITCLK and LRCLK. Each SAIF has
two source options: from external device through SAIF0 clock pins, from external device
through SAIF1 clock pins.
See
how to configure them for operation.
The SAIF contains a four-entry FIFO for each channel pair that buffers data between the
SAIF and the on-chip or off-chip RAM buffer used to supply or collect serial PCM audio
data. Both the SAIF's register and DMA interface are clocked by APBX clock. To ensure
the SAIF FIFO does not overrun or underrun, the minimum APBX clock frequency to
sample rate frequency ratio is 22:1. Therefore, if the sample rate is configured to 192 KHz,
then APBX must be set to 4.224 MHz or greater.
35.2.2 Transmit Operation
If the APBX DMA is to supply PCM data to the SAIF FIFO, the user first configures its
corresponding DMA channel and initializes the buffer(s) of PCM data that are to be played.
Next the SAIF control register is initialized, selecting the frame format and number of
channel pairs, clearing the CLKGATE bit, and setting the RUN bit.
Once running, the BITCLK, LRCLK, and optional MCLK pins begin to transition, and null
data is output to the off-chip analog DAC. The SAIF DMA interface requests PCM samples
until the FIFO(s) is/are filled, and continues to request a sample (or sample pair for 16-bit
operation) whenever an empty FIFO entry is available. Once valid PCM data resides within
the bottom of the front channel pair FIFO, the current null sample left/right pair(s) are
allowed to complete. At this point, the serialization frame control logic begins to output the
first valid left sample.
Freescale Semiconductor, Inc.
HW_SAIF_CLKMUX_SEL
Pin Control and GPIO Overview
Table 35-2. HW_DIGCTL_CTRL_SAIF_CLKMUX_SEL Programming
00
01
10
11
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
SAIF0_BITCLK_IN,
SAIF0_LRCLK_IN
SAIF0 Clock pins
SAIF1 Clock pins
SAIF0 Clock pins
SAIF1 Clock pins
for instructions on which pins the two SAIFs use and
Module Port
SAIF1_BITCLK_IN,
SAIF1_LRCLK_IN
SAIF1 Clock pins
SAIF0 Clock pins
SAIF0 Clock pins
SAIF1 Clock pins
Chapter 35 Serial Audio Interface (SAIF)
CROSSINPUT
EXTMSTR0
EXTMSTR
DIRECT
MODE
2207