MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 97

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Each layer of the AHB bus allows one active transaction at a time. A transaction is initiated
by a master, controlled by an arbiter, and serviced by the slave at the corresponding address.
A transaction can be as short as a single byte, or as long as a CPU cache line (32 bytes).
For the USB, a transaction can be much longer, up to 512 bytes.
AHB bus clock is named as the abbreviated "HCLK" or "clk_h" in the reference manual.
1.3.2.3 APB Buses
There are two APB buses on the i.MX28:
The “H” in APBH denotes that the APBH is synchronous to AHB's HCLK, as compared
to APBX, which runs on the crystal-derived XCLK. The APBX bus clock is named as the
abbreviated "XCLK" or "clk_x" in the reference manual.
The ARM926 data bus connects to all the slaves in the system, including RAMs, ROMs,
bridge slaves, USB and Ethernet slaves.
1.3.3 On-Chip RAM and ROM
The device includes 128 KB of on-chip RAM (OCRAM) implemented as four physical
banks. It adopts a 4-port, word interleaved topology to maximize performance in a multi-layer
bus system.
The device also includes 128 KB of on-chip mask-programmable ROM. The ROM contains
initialization code written by Freescale Inc. to handle the initial boot and hardware
initialization. Software in this ROM offers a large number of boot configuration options,
including manufacturing boot modes for burn-in and tester operation.
Freescale Semiconductor, Inc.
• Default first-level page table
• Two APB bridges
• APBH - The APBH (H DMA) is an AMBA2 APB system peripheral bus. This bus
• APBX - The APBX (X DMA) is an AMBA2 APB system peripheral bus. This bus is
comprises of the APBH peripherals such as those accessed through the APBH DMA
engine. The APBH peripherals are typically high-speed I/Os.
asynchronous to other system buses. This bus comprises of the APBX peripherals such
as those accessed through the APBX DMA engine. The APBX peripherals are typically
low speed I/Os or analog control related.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Chapter 1 Product Overview
97