MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1360

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
1360
8001_C2C0
8001_C2D0
8001_C2E0
8001_C3A0
8001_C3B0
8001_C3C0
8001_C3D0
8001_C3E0
8001_C2F0
8001_C300
8001_C310
8001_C330
8001_C370
8001_C380
8001_C390
8001_C3F0
8001_C500
8001_C510
8001_C520
8001_C530
8001_C540
Absolute
address
(hex)
Debug Trap Range Low Address for AHB Layer 0
(HW_DIGCTL_DEBUG_TRAP_L0_ADDR_LOW)
Debug Trap Range High Address for AHB Layer 0
(HW_DIGCTL_DEBUG_TRAP_L0_ADDR_HIGH)
Debug Trap Range Low Address for AHB Layer 3
(HW_DIGCTL_DEBUG_TRAP_L3_ADDR_LOW)
Debug Trap Range High Address for AHB Layer 3
(HW_DIGCTL_DEBUG_TRAP_L3_ADDR_HIGH)
Freescale Copyright Identifier Register (HW_DIGCTL_FSL)
Digital Control Chip Revision Register (HW_DIGCTL_CHIPID)
AHB Statistics Control Register
(HW_DIGCTL_AHB_STATS_SELECT)
AHB Layer 1 Transfer Count Register
(HW_DIGCTL_L1_AHB_ACTIVE_CYCLES)
AHB Layer 1 Performance Metric for Stalled Bus Cycles
Register (HW_DIGCTL_L1_AHB_DATA_STALLED)
AHB Layer 1 Performance Metric for Valid Bus Cycles Register
(HW_DIGCTL_L1_AHB_DATA_CYCLES)
AHB Layer 2 Transfer Count Register
(HW_DIGCTL_L2_AHB_ACTIVE_CYCLES)
AHB Layer 2 Performance Metric for Stalled Bus Cycles
Register (HW_DIGCTL_L2_AHB_DATA_STALLED)
AHB Layer 2 Performance Metric for Valid Bus Cycles Register
(HW_DIGCTL_L2_AHB_DATA_CYCLES)
AHB Layer 3 Transfer Count Register
(HW_DIGCTL_L3_AHB_ACTIVE_CYCLES)
AHB Layer 3 Performance Metric for Stalled Bus Cycles
Register (HW_DIGCTL_L3_AHB_DATA_STALLED)
AHB Layer 3 Performance Metric for Valid Bus Cycles Register
(HW_DIGCTL_L3_AHB_DATA_CYCLES)
Default First Level Page Table Movable PTE Locator 0
(HW_DIGCTL_MPTE0_LOC)
Default First-Level Page Table Movable PTE Locator 1
(HW_DIGCTL_MPTE1_LOC)
Default First-Level Page Table Movable PTE Locator 2
(HW_DIGCTL_MPTE2_LOC)
Default First-Level Page Table Movable PTE Locator 3
(HW_DIGCTL_MPTE3_LOC)
Default First-Level Page Table Movable PTE Locator 4
(HW_DIGCTL_MPTE4_LOC)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_DIGCTL memory map (continued)
Register name
(in bits)
Width
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Freescale Semiconductor, Inc.
Reset value
0000_0000h
0000_0000h
0000_0000h
0000_0000h
6565_7246h
2800_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0001h
0000_0002h
0000_0003h
0000_0004h
19.4.34/1395
19.4.35/1396
19.4.36/1396
19.4.37/1397
19.4.38/1397
19.4.39/1398
19.4.40/1399
19.4.41/1400
19.4.42/1401
19.4.43/1401
19.4.44/1402
19.4.45/1403
19.4.46/1403
19.4.47/1404
19.4.48/1405
19.4.49/1406
19.4.50/1406
19.4.51/1407
19.4.52/1408
19.4.53/1409
19.4.54/1410
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