MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1072

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

EMI AHB and AXI Interface
14.4.5 AXI Write Response Channel
When a write request is accepted into the AXI interface, an entry will be created in the
Write-Response FIFO for that command. When a write response is ready, the response will
be returned to the AXI master.
Different masters may require this response at different stages of the write command. A
master that needs to quickly release the bus would optimally receive the completion response
as soon as the port has accepted the write command and all of the corresponding data.
Another master may wish to wait until the data has been accepted into the core logic, or
successfully written to memory.
Each AXI interface is configured with two signals that work together to determine when
an instruction is considered complete and the write completion response will be returned
to the master. These signals are axi_AWCACHE [0] and axi_AWCOBUF. The following
table details the relationship between these signals.
1072
axi_AWCACHE[0]
0
1
AXI Write Data Channel
AXI Read Command Channel
AXI Write Response Channel
AXI Write Command Channel
AXI Read Data Channel
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
axi_AWCOBUF
Irrelevant
0
Table 14-5. Write Response Types
Figure 14-4. AXI Interface FIFOs
Non-bufferable write command. Response is ready after the write data is
committed to memory.
Standard bufferable write command. Response is ready when the command
and all associated data have been received by the AXI data port. There is
no guarantee of data coherency across all AXI ports.
Response Information
Arbiter
Port
AXI
Resp
Array
AXI Interface
Write Data FIFO
Read Data FIFO
Command
FIFO
Synch
FIFO
1
Read/Write
Read/Write
Command
Freescale Semiconductor, Inc.
Queues
Queue
Arbiter
Data
Bus
&
&