MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1576

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Initialization/Application Information
Soft reset is synchronous and has to follow an internal request/acknowledge procedure
across clock domains. Therefore, it may take some time to fully propagate its effects. The
SOFT_RST bit remains asserted while soft reset is pending, so software can poll this bit to
know when the reset has completed. Also, soft reset can not be applied while clocks are
shut down in any of the low power modes. The low power mode should be exited and the
clocks resumed before applying soft reset.
The clock source (CLK_SRC bit) should be selected while the module is in Disable Mode.
After the clock source is selected and the module is enabled (MDIS bit negated), FlexCAN
automatically goes to Freeze Mode. In Freeze Mode, FlexCAN is un-synchronized to the
CAN bus, the HALT and FRZ bits in MCR Register are set, the internal state machines are
disabled and the FRZ_ACK and NOT_RDY bits in the MCR Register are set. The Tx pin
is in recessive state and FlexCAN does not initiate any transmission or reception of CAN
frames. Note that the Message Buffers and the Rx Individual Mask Registers are not affected
by reset, so they are not automatically initialized.
For any configuration change/initialization it is required that FlexCAN is put into Freeze
Mode (see
the FlexCAN module:
1576
• i.MX28 level hard reset using ipg_hard_async_reset_b, which resets all memory mapped
• i.MX28 level soft reset, which resets some of the memory mapped registers
• SOFT_RST bit in MCR, which has the same effect as the i.MX28 level soft reset
• Initialize the Module Configuration Register
• Initialize the Control Register
registers asynchronously
synchronously
• Enable the individual filtering per MB and reception queue features by setting the
• Enable the warning interrupts by setting the WRN_EN bit
• If required, disable frame self reception by setting the SRX_DIS bit
• Enable the FIFO by setting the FEN bit
• Enable the abort mechanism by setting the AEN bit
• Enable the local priority feature by setting the LPRIO_EN bit
• Determine the bit timing parameters: PROPSEG, PSEG1, PSEG2, RJW
BCC bit
Freeze
Mode). The following is a generic initialization sequence applicable to
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.