MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1978

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
31.7.14 Host Control Capability Parameters (EHCI-Compliant) Register
This register identifies multiple mode control (time-base bit functionality) addressing
capability. The default value of this register is 0x00000006.
Address:
1978
Reset
Reset
Bit
Bit
W
W
R
R
RSVD2
RSVD0
31 16
EECP
Field
15 8
ASP
7 4
IST
3
2
31
15
0
0
HW_USBCTRL_HCCPARAMS
0108h
(HW_USBCTRL_HCCPARAMS)
30
14
0
0
Reserved.
EHCI Extended Capabilities Pointer.
Default = 0. This optional field indicates the existence of a capabilities list.
A value of 0x00 indicates no extended capabilities are implemented.
A non-zero value in this register indicates the offset in PCI configuration space of the first EHCI extended
capability. The pointer value must be 0x40 or greater if implemented to maintain the consistency of the PCI
header defined for this class of device.
Isochronous Scheduling Threshold.
Indicates, relative to the current position of the executing host controller, where software can reliably update
the isochronous schedule.
When bit 7 is 0, the value of the least significant 3 bits indicates the number of micro-frames a host controller
can hold a set of isochronous data structures (one or more) before flushing the state.
When bit 7 is a 1, then host software assumes the host controller may cache an isochronous data structure
for an entire frame.
Reserved.
Asynchronous Schedule Park Capability.
Default = 1.
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_USBCTRL_HCCPARAMS field descriptions
28
12
0
0
EECP
27
11
0
0
26
10
0
0
8008_0000h base + 108h offset = 8008_
25
0
0
9
24
0
0
8
RSVD2
Description
23
0
0
7
22
0
0
6
IST
21
0
5
0
20
0
4
0
Freescale Semiconductor, Inc.
RSVD0
19
0
0
3
ASP
18
0
1
2
PFL
17
0
1
1
ADC
16
0
0
0