MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1591

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

25.6.15 Rx Individual Mask Registers (HW_CAN_RXIMRn)
The default value of this register is 0x00000000. There are 64 Rx Individual Mask registers
( RXIMR0¨RXIMR63) n denotes the number from 0 to 63.
These registers are used as acceptance masks for ID filtering in Rx message buffers and the
FIFO. If the FIFO is not enabled, one mask register is provided for each available message
buffer, providing ID masking capability on a per message buffer basis. When the FIFO is
enabled (FEN bit in the MCR is set), the first 8 mask registers apply to the 8 elements of
the FIFO filter table (on a one-to-one correspondence), while the rest of the registers apply
to the regular message buffers, starting from message buffer 8. The individual Rx mask
registers are implemented in RAM, so they are not affected by reset and must be explicitly
initialized prior to any reception. Furthermore, they can only be accessed by the ARM while
the module is in freeze mode. Outside of freeze mode, write accesses are blocked and read
accesses return all zeros. Furthermore, if the BCC bit in the MCR is cleared, any read or
write operation to these registers results in an access error.
Address:
Re-
Freescale Semiconductor, Inc.
set
Bit
W
R
31
0
Field
31 0
Field
31 0
MBn
MI
30
0
29
0
HW_CAN_RXIMRn
28
0
These registers are used as acceptance storage for messages.
These registers are used as acceptance masks for ID filtering in Rx message buffers and the FIFO.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
23
0
HW_CAN_RXIMRn field descriptions
8003_2000h base + 880h offset = 8003_2880h
22
0
HW_CAN_MBn field descriptions
21
0
20
0
19
0
18
0
17
0
16
0
MI
15
0
Description
Description
14
0
13
0
Chapter 25 Controller Area Network (FlexCAN)
12
0
11
0
10
0
0
9
0
8
0
7
0
6
0
5
0
4
3
0
0
2
0
1
1591
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