MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2015
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MCIMX286CVM4B
Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(70 pages)
2.MCIMX283DVM4B.pdf
(2 pages)
3.MCIMX283DVM4B.pdf
(2327 pages)
4.MCIMX283DVM4B.pdf
(20 pages)
Specifications of MCIMX286CVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
- MCIMX283DVM4B PDF datasheet
- MCIMX283DVM4B PDF datasheet #2
- MCIMX283DVM4B PDF datasheet #3
- MCIMX283DVM4B PDF datasheet #4
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- Download datasheet (17Mb)
31.7.38 Endpoint Status Register (HW_USBCTRL_ENDPTSTAT)
This register is used in device mode only.
endpoint ready
Address:
Re-
Freescale Semiconductor, Inc.
set
Bit
W
R
31
0
RSVD1
31 24
23 16
ETBR
Field
Field
30
0
29
0
HW_USBCTRL_ENDPTSTAT
RSVD1
28
0
FERB[5] = Endpoint 5.
FERB[4] = Endpoint 4.
FERB[3] = Endpoint 3.
FERB[2] = Endpoint 2.
FERB[1] = Endpoint 1.
FERB[0] = Endpoint 0.
Reserved.
Endpoint Transmit Buffer Ready.
One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a 1 by the
hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register.
There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating
ready. This delay time varies based upon the current USB traffic and the number of bits set in the
ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the
ENDPTFLUSH register.
Note: These bits will be momentarily cleared by hardware during hardware endpoint re-priming operations
when a dTD is retired, and the dQH is updated.
ETBR[7] = Endpoint 7.
ETBR[6] = Endpoint 6.
ETBR[5] = Endpoint 5.
ETBR[4] = Endpoint 4.
ETBR[3] = Endpoint 3.
ETBR[2] = Endpoint 2.
ETBR[1] = Endpoint 1.
27
HW_USBCTRL_ENDPTFLUSH field descriptions (continued)
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
HW_USBCTRL_ENDPTSTAT field descriptions
24
0
23
0
22
0
21
0
ETBR
20
0
8008_0000h base + 1B8h offset = 8008_01B8h
19
0
18
0
17
0
Chapter 31 USB High-Speed On-the-Go Host Device Controller
16
0
15
0
Description
Description
14
0
13
0
RSVD0
12
0
11
0
10
0
0
9
0
8
0
7
0
6
0
5
ERBR
0
4
3
0
0
2
0
1
2015
0
0
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