MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1479

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Immediately after reset, it will take approximately three milliseconds for the copy controller
to complete the copy process from the analog domain to the digital domain. Software cannot
rely on the contents of the seconds counter, alarm, or persistent bits until this copy is
complete. Therefore, software must wait until all bits of interest in the
HW_RTC_STAT_STALE_REGS field have been reset to 0 by the copy controller before
reading the initial state of these values (see
updated is Persistent 0, 1, 2, 3, 4, 5, Alarm, Seconds. (This list is in bitfield order, from LSB
to MSB, as they would appear in the STALE_REGS and NEW_REGS bitfields of the
HW_RTC_STAT register. For example, the Seconds register corresponds to STALE_REGS
or NEW_REGS containing 0x80.)
Freescale Semiconductor, Inc.
Figure 22-1. RTC, Watchdog, Alarm, and Persistent Bits Block Diagram
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
APBX Master
AHB Slave
ARM Core
Figure 22-2. RTC Initialization Sequence
RTC/Watchdog/Alarm/
Shared DMA
Persistent I/O
32-Bit RTC Shadow Counter
32-Bit Shadow Persistent 2
32-Bit Shadow Persistent 3
32-Bit Shadow Persistent 4
32-Bit Shadow Persistent 5
32-Bit Shadow Persistent 0
32-Bit Shadow Persistent 1
HW_RTC_CTRL_CLKGATE_WRITE (BM_RTC_CTRL_CLKGATE);
AHB
AHB-to-APBX Bridge
HW_RTC_CTRL_SFTRST_WRITE (BM_RTC_CTRL_SFTRST);
AHB Master
32-Bit Alarm Shadow
SRAM
1 Hz
rtc_init
Return
Figure
Chapter 22 Real-Time Clock Alarm Watchdog Persistent Bits
controller
1 kHz
Copy
Divide
by n
Remove soft reset and clock gate.
This releases the copy controller.
Call during initialization
22-2). The order in which registers are
Crystal Power and Clock Domain
Divide by appropriate value
32-Bit Master Persistent 0
32-Bit Master Persistent 1
32-Bit Master Persistent 2
32-Bit Master Persistent 3
32-Bit Master Persistent 4
32-Bit Master Persistent 5
fixed divide by 24000
32-Bit RTC Seconds
32-Bit Alarm Master
==
Alarm Event
1 Hz
32.768 or
32.000
XTAL
Osc.1
kHz
24-MHz
XTAL
Osc.
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