MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1729

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Chapter 27
Inter IC (I2C)
27.1 I
The I
host controllers. This interface provides a standard speed (up to 100 kbps), and a fast speed
(up to 400 kbps) I
or I
tuner, cell phone baseband chip connection, and so on.
The I
As implemented on the i.MX28, the I
Freescale Semiconductor, Inc.
• The I
• The I
• PIO mode, that is, soft DMA mode is supported.
• PIO Queue mode is supported. This mode allows software to queue up multiple
• The I
2
generates the clock (I2C_SCL) and initiates transactions on the data line (I2C_SDA).
transactions. Data on the I
three bytes plus address) can be easily triggered using only PIO operations, that is, no
DMA setup required.
commands and supporting data for later automatic execution.
transactions. It also has a programmable 7-bit address that defaults to 0x43 = 7'b1000011
for slave transactions. As seen in the 8-bit device address byte, this address corresponds
to 0x86 where the least significant bit (LSB) is the R/W bit. 10-bit address is not
supported in slave mode.
C slave mode. Typical applications for the I
2
2
C is a standard two-wire serial interface used to connect the chip with peripherals or
C port supports multi-master configurations.
2
2
2
2
C Overview
C block can be configured as either a master or slave device. In master mode, it
C block packs/unpacks data into 8-, 16-, 24-, or 32-bit words for DMA
C block support programmable 7-bit and 10-bit device addresses for master
2
C connection to multiple devices with the chip acting in either I
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
2
C bus is always byte-oriented. Short transmission (up to
2
C block includes the following functions:
2
C bus include: EEPROM, LED/LCD, FM
2
C master
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