MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1866

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
1866
Reset
INITIALIZING
MEM_FULL_
DEQUEUE_
MEM_FULL
AVAILABLE
NO_CELL_
Bit
W
RSRVD2
RSRVD1
RSRVD0
R
CELLS_
GRANT
BUSY_
LATCH
LATCH
31 24
23 16
Field
15 7
5 4
6
3
2
1
0
15
0
14
0
Reserved bits. Write as 0.
Real-time indication of currently available cells in memory.
Reserved bits. Write as 0.
Indication of if currently inputs are de-queued. Should be set always and is cleared when the memory
becomes full (see also mem_full indication).
Note: the bit is cleared upon reset, however set shortly after when the memory manager has completed
initialization.
Reserved bits. Write as 0.
Latched version of mem_full. Is kept set even when mem_full is cleared again.
The bit is cleared when the register is written.
Current memory full indication. The memory is full when less than the programmed minimum cell threshold
is available in memory. This is not an error and the memory controller is working fine.
It just indicates that the switch does no longer serve its input ports to avoid memory overrun (no_cell error).
Set, when memory has exceeded the maximum available number of cells. The event is latched and the bit
stays set if the event is no longer active.
This is a fatal error and must never happen during operation.The minimum cells threshold must be increased
if it happens.
The bit is always set after reset (during initialization) and must be cleared when the busy initialization (see
bit 0) indication is cleared.
IMPORTANT NOTE: When this bit is set any time during operation (after initialization completed) the switch
is in an inoperable state and must be reset completely to restore correct operation. If such an event happens,
the QMGR_MINCELLS setting must be increased during initialization to avoid such situation.
The bit is cleared when the register is written.
When set (1), Memory controller is initializing. The initialization is only preparing the internal data structures
within the controller, it does not initialize the shared memory used for frame storage as this is not required.
It is asserted after reset and stays set until the memory controller is ready to store frames. The switch must
not be enabled before initialization of the memory controller has been completed.
13
0
HW_ENET_SWI_OQMGR_STATUS field descriptions
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
12
0
RSRVD1
11
0
10
0
0
9
0
8
Description
0
7
1
6
RSRVD0
5
0
4
0
Freescale Semiconductor, Inc.
1
3
0
2
1
1
0
0