MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1816

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Modes of Operation
29.4.5.3.3 Mode 1: Strip Mode
In Strip mode, all the Tags (Single or double) are removed from incoming frame
29.4.5.3.4 Mode 2: Tag Thru Mode
In Tag Thru mode, the inner Tag is passed thru while the outer Tag is removed for a double
Tagged frame. The following rules apply:
29.4.5.3.5 Mode 3: Transparent Mode
In Transparent mode, single tagged frame is kept unchanged. The following rules apply:
29.4.6.1 Overview
When a Frame is received on an input port, several information are extracted from the frame
as the Ethernet MAC Address, VLAN tag and IP Headers to determine the Frame Type and
perform the relevant Classification actions.
In addition, the MAC Address table can provide a priority indication for the destination
MAC address if the switch management has programmed the address table accordingly
(static entry).
The Frame is classified into four priority levels (priority0=lowest, priority3=highest) and
is eventually queued in the corresponding priority queue at the output port.
29.4.6.2 VLAN Priority Look-Up
On each port, an 8 entry programmable priority table is implemented. The registers
VLAN_PRIORITY0..2 contain the priority mapping for port n.
The switch uses 3-Bits from the VLAN tag information (3-bit VLAN priority) to extract
the corresponding bits from the Table, which indicates which priority the Frame should be
finally classified.
The index in the mapping table is the 3 bits of the first octet of the VLAN Tag Data with
bit 5 (prio0) being the LSB and Bit 7 (prio(2)) being the MSB.
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• When a single Tagged frame is received, strip the tag from the frame.
• When a double Tagged frame is received, strip the outer tag from the frame.
• When a single Tagged frame is received, frame is kept unchanged.
• When a double Tagged frame is received, strip the outer tag from the frame.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.