MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2167

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MCIMX286CVM4B

Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r

Specifications of MCIMX286CVM4B

Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
34.4.18 PXP S0 Color Key Low (HW_PXP_S0COLORKEYLOW)
This register contains the color key low value for the S0 buffer.
When processing an image, the if the PXP finds a pixel in the background image with a
color that falls in the range from the S0COLORKEYLOW to S0COLORKEYHIGH range,
it will substitute the color found in the matching overlay. If no overlay is present or if the
overlay also matches its colorkey range, the s0background color is used.
EXAMPLE
HW_PXP_S0COLORKEYLOW_WR (0x008000); // medium green and
HW_PXP_S0COLORKEYHIGH_WR(0x00FF00); // light green
Address:
Re-
Freescale Semiconductor, Inc.
set
Bit
W
R
ENABLED
POINTER
31
0
RSVD1
RSVD
31 24
PIXEL
Field
31 2
Field
23 0
30
1
0
0
29
0
HW_PXP_S0COLORKEYLOW 8002_A000h base + 180h offset = 8002_A180h
RSVD1
28
0
A pointer to a data structure containing register values to be used when processing the next frame.
The pointer must be 32-bit aligned and should reside in on-chip or off-chip memory.
Reserved, always set to zero.
Indicates that the next frame functionality has been enabled. This bit reflects the status of the hardware
semaphore indicating that a reload operation is pending at the end of the current frame.
Reserved, always set to zero.
Low range of RGB color key applied to S0 buffer. To disable S0 colorkeying, set the low colorkey to 0xFFFFFF
and the high colorkey to 0x000000.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
HW_PXP_S0COLORKEYLOW field descriptions
24
0
23
1
HW_PXP_NEXT field descriptions
22
1
21
1
20
1
// colorkey values between
19
1
18
1
17
1
16
1
15
1
Description
Description
14
1
13
1
PIXEL
12
1
11
1
10
1
1
9
Chapter 34 Pixel Pipeline (PXP)
1
8
1
7
1
6
1
5
1
4
3
1
1
2
1
1
2167
1
0

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