MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1731

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Pullup resistors are required on both of the I
(pulldown only). Typically, external 2k resistors are used to pull the signals up to VddIO
for normal and fast speeds.
27.2.1 I
The I
generated by the completion of a DMA command in the APBX DMA. DMA interrupts are
the reporting mechanism for I
or partial completions are signaled by interrupts generated within the I
If I
one of the events listed in
Freescale Semiconductor, Inc.
Slave Address
Slave Stop
Oversize Xfer
Early Termination
Master Loss
No Slave Ack
SOURCE
• I2C_SDA: I
• I2C_SCL: I
2
C interrupts are enabled, a level-sensitive interrupt are signaled to the processor upon
data.
2
C port can be used in either interrupt-driven or polled modes. An interrupt can be
Table 27-1. I
2
C Interrupt Sources
SLAVE_IRQ
SLAVE_STOP_IRQ
OVER-
SIZE_XFER_TERM_IRQ
EARLY_TERM_IRQ
MASTER_LOSS_IRQ
NO_SLAVE_ACK_IRQ
Bit Name
2
2
C Serial Clock This pin carries the clock used to time the address and
C Serial Data This pin carries all address and data bits.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
2
C Slave and Master Interrupt Condition in HW_I2C_CTRL1
Table
2
C transactions that terminate normally. Abnormal terminations
27-1.
This interrupt is generated when an address match occurs. It indicates that
the CPU should read the captured RW bit from the I
termine the type of DMA to use for the data transfer phase.
This interrupt is generated when a stop condition is detected after a slave
address has been matched.
The DMA and I
the data phase is not terminated within this transfer size then oversize
transfer processing goes into effect and the CPU is alerted through this in-
terrupt. This interrupt is only used in slave mode.
The DMA and I
the data phase is terminated before this transfer size then early termination
processing goes into effect and the CPU is alerted through this interrupt.
A master begins transmission on an idle I
If it ever attempts to send a one on the line and notes that a zero has been
sent instead, then it notes that it has lost mastership of the I
ates its transfer and reports the condition to the CPU through this interrupt.
This detection only happens on master transmit operations.
When a start condition is transmitted in master mode, the next byte contains
an address for a targeted slave. If the targeted slave does not acknowledge
the address byte, then this interrupt is set, no further I
cessed, and the I
Description
2
C lines as all of the I
2
2
C controller are initialized for an expected transfer size. If
C controller are initialized for an expected transfer size. If
2
C bus returns to the idle state.
2
2
C drivers are open drain
C bus and monitors the data line.
2
C controller.
Chapter 27 Inter IC (I2C)
2
C address byte to de-
2
C protocol is pro-
2
C bus. It termin-
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