MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 956

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

OTP eFuse and Persistent Bit Definitions
956
HW_OCOTP_ROM4:0x8002C1E0:3:0
HW_OCOTP_ROM7:0x8002C210:23
HW_OCOTP_ROM7:0x8002C210:22
HW_OCOTP_ROM7:0x8002C210:21:20
HW_OCOTP_ROM7:0x8002C210:19:12
HW_OCOTP_ROM7:0x8002C210:8
HW_OCOTP_ROM7:0x8002C210:7:4
HW_OCOTP_ROM7:0x8002C210:3
HW_OCOTP_ROM7:0x8002C210:2
HW_OCOTP_ROM7:0x8002C210:1
HW_OCOTP_ROM7:0x8002C210:0
eFuse
Bank:Address:Bit
Bank:Address:Bit
eFuse
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Table 12-8. General ROM Bit in ROM7 OCOTP Bank
NAND_ROW_ADDRESS_BYTES
NAND Flash row address cycles.
Reserved
ARM_PLL_DISABLE
PLL is enabled by default, the ARM clock will run at 240 MHz. If blown, the PLL
will be disabled and ROM will run at 24 MHz during the boot except for USB mode.
HAB_CONFIG
00 = Reserved
01 = HAB_OPEN, default mode
Other = HAB_CLOSED
Reserved
ENABLE_SSP_12MA_DRIVE
Blow to force SSP pins to drive 12 mA, default is 4 mA.
Reserved.
I2C_USE_400 KHZ
Blow to force the I
KHz is the default.
ENABLE_ARM_ICACHE
Blow to enable the ARM 926 ICache during boot.
MMU_DISABLE
0 =MMU and D-Cache are enabled in default to speed up HAB functions execution
speed.
1 =MMU and D-Cache are disabled during boot if blown.
ENABLE_PIN_BOOT_CHECK
Blow to enable boot loader to first test the LCD_RS pin to determine if the pin boot
mode is enabled. If this bit is blown and LCD_RS is pulled high, then boot mode
is determined by the state of LCD_D[5:0] pins. If this bit is not blown, skip testing
the LCD_RS pin and go directly to determine the boot mode by reading the state
of LCD_D[5:0].
eFuse Function
2
C to be programmed by the boot loader to run at 400 KHz. 100
eFuse Function
Freescale Semiconductor, Inc.