MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2293

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

38.5.11 LRADC 5 Result Register (HW_LRADC_CH5)
The LRADC result register returns the 12-bit result for low resolution analog to digital
converter channel five.
HW_LRADC_CH5: 0x0A0
HW_LRADC_CH5_SET: 0x0A4
HW_LRADC_CH5_CLR: 0x0A8
HW_LRADC_CH5_TOG: 0x0AC
The Result register contains the most recent conversion results for one channel of the
LRADC. Note that each channel can be converted at an independent rate. The TOGGLE
bit is used to debug missed conversion cycles. When using oversampling, the channel must
be individualy scheduled for conversion N times for when N samples are required before
an interrupt is generated. This is most easily accomplished by using one of the LRADC
Delay Channels.
EXAMPLE
if (HW_LRADC_CHn(5).TOGGLE == 1) { } // Toggle is high.
// ...
unsigned long channelAverage;
HW_LRADC_CHn_WR(5, (BF_LRADC_CHn_ACCUMULATE(1)
// ... setup Delay channel (see HW_LRADC_DELAY0 through 3)
while (HW_LRADC_CTRL1.LRADC5_IRQ != BV_LRADC_CTRL1_LRADC5_IRQ__PENDING)
{
}
channelAverage = HW_LRADC_CHn(5).VALUE / 5;
Address:
Freescale Semiconductor, Inc.
Reset
// Wait for interrupt.
Bit
W
R
31
0
HW_LRADC_CH5
30
0
29
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
BF_LRADC_CHn_NUM_SAMPLES(5)
BF_LRADC_CHn_VALUE(0) ) );
28
0
8005_0000h base + A0h offset = 8005_00A0h
NUM_SAMPLES
27
0
26
0
Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface
25
0
24
0
| // Enable accumulation mode.
| // Set samples to five.
23
0
// Clear accumulator.
22
0
21
RSRVD1
0
20
0
19
0
18
0
VALUE[17:16]
17
0
2293
16
0