MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1799

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

28.4.14 PWM Channel 6 Active Register (HW_PWM_ACTIVE6)
The PWM Channel 6 Active Register specifies the active time and inactive time for Channel
6.
HW_PWM_ACTIVE6: 0x0d0
HW_PWM_ACTIVE6_SET: 0x0d4
HW_PWM_ACTIVE6_CLR: 0x0d8
HW_PWM_ACTIVE6_TOG: 0x0dC
EXAMPLE
HW_PWM_ACTIVEn_WR(6, 0x000000ff);
Address:
Re-
Freescale Semiconductor, Inc.
set
Bit
W
ACTIVE_STATE
R
INACTIVE_
31
0
PERIOD
STATE
19 18
17 16
Field
15 0
30
0
29
0
HW_PWM_ACTIVE6
28
0
0x6
0x7
The logical inactive state that is mapped to the PWM output signal. Note that the undefined state of 0x1 is
mapped to high-impedance.
0x0
0x2
0x3
The logical active state is mapped to the PWM output signal. Note that the undefined state of 0x1 is mapped
to high-impedance.
0x0
0x2
0x3
Number of divided clock cycles in the entire period of the PWM waveform, minus 1. For example, to obtain
6 clock cycles in the actual period, set this field to 5.
27
0
26
0
DIV_256 — Divide by 256.
DIV_1024 — Divide by 1024.
HI_Z — Inactive state sets PWM output to high-impedance.
0 — Inactive state sets PWM output to 0 (low).
1 — Inactive state sets PWM output to 1 (high).
HI_Z — Active state sets PWM output to high-impedance.
0 — Active state sets PWM output to 0 (low).
1 — Active state sets PWM output to 1 (high).
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_PWM_PERIOD5 field descriptions (continued)
25
0
INACTIVE
24
0
23
0
8006_4000h base + D0h offset = 8006_40D0h
22
0
21
0
20
0
// Set active and inactive counts
19
0
18
0
17
0
16
0
15
0
Description
14
0
Chapter 28 Pulse-Width Modulator (PWM) Controller
13
0
12
0
11
0
10
0
0
9
ACTIVE
0
8
0
7
0
6
0
5
0
4
3
0
0
2
0
1
1799
0
0