MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1283

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

command
read[3].dma_bar = dma_error_handler;
error handler
//----------------------------------------------------------------------------
// Descriptor 5: read 4K page plus 65 byte meta-data Nand data
//
//----------------------------------------------------------------------------
read[4].dma_nxtcmdar = &read[5];
read[4].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT
taking over
read[4].dma_bar = NULL;
// 6 words sent to the GPMI
read[4].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, READ)
blocks
read[4].gpmi_compare = NULL;
eccctrl
// GPMI ECCCTRL PIO This launches the 4K byte transfer through BCH's
// bus master. Setting the ECC_ENABLE bit redirects the data flow
// within the GPMI so that read data flows to the BCH engine instead
// of flowing to the GPMI's DMA channel.
read[4].gpmi_eccctrl = BV_FLD(GPMI_ECCCTRL, ECC_CMD,
mode
read[4].gpmi_ecccount = BF_GPMI_ECCCOUNT_COUNT(4096+218);
read[4].gpmi_data_ptr = &read_payload_buffer;
read[4].gpmi_aux_ptr = &read_aux_buffer;
aux area +
//----------------------------------------------------------------------------
// Descriptor 6: disable ECC block
//----------------------------------------------------------------------------
read[5].dma_nxtcmdar = &read[6];
read[5].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT
Freescale Semiconductor, Inc.
CS used
1 aux block
for both
and send it to ECC block (DATA)
BF_APBH_CHn_CMD_WAIT4ENDCMD
BF_APBH_CHn_CMD_IRQONCMPLT
BF_APBH_CHn_CMD_CHAIN
BV_FLD(APBH_CHn_CMD, COMMAND, DMA_SENSE);
BF_APBH_CHn_CMD_CMDWORDS
BF_APBH_CHn_CMD_WAIT4ENDCMD
BF_APBH_CHn_CMD_SEMAPHORE
BF_APBH_CHn_CMD_NANDWAIT4READY(0)
BF_APBH_CHn_CMD_NANDLOCK
BF_APBH_CHn_CMD_IRQONCMPLT
BF_APBH_CHn_CMD_CHAIN
BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER);
BF_APBH_CHn_CMD_CMDWORDS
BF_APBH_CHn_CMD_SEMAPHORE
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
BF_GPMI_CTRL0_CS
BV_FLD(GPMI_CTRL0, WORD_LENGTH,
BV_FLD(GPMI_CTRL0, LOCK_CS,
BV_FLD(GPMI_CTRL0, ADDRESS,
BF_GPMI_CTRL0_ADDRESS_INCREMENT
BF_GPMI_CTRL0_XFER_COUNT
BV_FLD(GPMI_ECCCTRL, ENABLE_ECC, ENABLE)
BF_GPMI_ECCCTRL_BUFFER_MASK
(1)
(0)
(1)
(0)
(6)
(1)
(0)
(1)
(0)
(1)
(0)
(3)
(0)
Chapter 16 20-BIT Correcting ECC Accelerator (BCH)
(2)
| // no dma transfer
| // send 6 words to GPMI
| // wait for command to finish before
|
|
| // prevent other DMA channels from
| // ECC block generates BCH interrupt
| // follow chain to next command
8_BIT)
DISABLED)
NAND_DATA)
(0)
(4096+218);
// field not used but necessary to set
(0X1FF);
| // wait for command to finish before
// point to the next descriptor
//
//
DECODE_8_BIT) |
| // no dma transfer
| // send 3 words to GPMI
|
// if sense check fails, branch to
|
|
// point to the next descriptor
//
on completion
// data and aux blocks.
// ECC block handles transfer
// read all 8 data blocks and
|
continuing
// specify number of bytes
//
// pointer for the 4K byte
//
// pointer for the 65 byte
// parity and syndrome bytes
// follow chain to next
// perform a sense check
// no DMA transfer,
// field not used
|
|
|
|
|
continuing
// must correspond to NAND
|
// read from the NAND
// eight 512 byte data
// metadata, and parity
data area
// enable ECC module
// specify t = 8
read from NAND
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