MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 501

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

DMA_WRITE operations copy data bytes to the system memory (on-chip RAM or SDRAM)
from the associated peripheral. Each peripheral has a target PADDR value that it expects
to receive DMA bytes. This association is synthesized in the DMA. The DMA_WRITE
transfer uses the BUFFER_ADDRESS word in the command structure to point to the
beginning byte to write data from the peripheral.
DMA_READ operations copy data bytes to the APB peripheral from the system memory.
The DMA engine contains a shared byte aligner that aligns bytes from system memory to
or from the peripherals. Peripherals always assume little-endian-aligned data arrives or
departs on their 32-bit APB. The DMA_READ transfer uses the BUFFER_ADDRESS
word in the command structure to point to the DMA data buffer to be read by the
DMA_READ command.
The NO_DMA_XFER command is used to write PIO words to a device without performing
any DMA data byte transfers.
As each DMA command completes, it triggers the DMA to load the next DMA command
structure in the chain. The normal flow list of DMA commands is found by following the
NEXTCMD_ADDR pointer in the DMA command structure. If the wait-for-end-command
bit (WAIT4ENDCMD) is set in a command structure, then the DMA channel waits for the
device to signal completion of a command by toggling the apx_endcmcd signal before
proceeding to load and execute the next command structure. Then, if
DECREMENT_SEMAPHORE is set, the semaphore is decremented after the end command
is seen.
A detailed bit-field view of the DMA command structure is shown in the following table,
which shows a field that specifies the number of bytes to be transferred by this DMA
command. The transfer count mechanism is duplicated in the associated peripheral, either
as an implied or as a specified count in the peripheral.
Freescale Semiconductor, Inc.
31
COMMAND
30
DMA
10
11
29
28
27
DMA_READ. Perform any requested PIO word transfers, and then perform a DMA transfer to the peripheral
for the specified number of bytes.
Reserved
Usage
Table 7-3. DMA Channel Command Word in System Memory
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i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
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20
NEXT_COMMAND_ADDRESS
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17
Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA)
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