MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1636

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

IP Accelerator Functions
The TCP/UDP length value is the length of the TCP or UDP datagram, which is equal to
the payload of an IP datagram. It is derived by subtracting the IP header length from the
complete IP datagram length that is given in the IP header (IPv4) or directly taken from the
IP header (IPv6). The protocol field is the corresponding value from the IP header and 'zero'
is filled with zeroes.
For IPv6, the complete 128 bit addresses are considered. The next header value identifies
the upper layer protocol (TCP or UDP) and may differ from the IPv6 header's actual next
header value. if the extension headers are inserted before the protocol header.
The checksum calculation uses 16-bit words in network byte order: The first byte
sent/received is the most significant byte and the second byte sent/received is the least
significant byte of the 16-bit value to add to the checksum. If the frame ends on an odd
number of bytes, a zero byte is appended for checksum calculation only (not actually
transmitted).
26.3.11.2 Additional Padding Processing
Any Ethernet frame according to IEEE 802.3 must have a minimum length of 64 octets.
The MAC usually removes padding on receive, when a frame with length information is
received. As IP frames have a type value instead of the length, the MAC will not remove
padding for short IP frames, as it is not aware of the frame contents.
The IP Accelerator function can be configured to remove the Ethernet padding bytes that
might follow the IP datagram.
On transmit, the MAC automatically ensures to add padding as necessary to fill any frame
to a length of 64.
26.3.11.3 32-bit Ethernet Payload Alignment
The data FIFOs allow inserting two additional arbitrary bytes in front of a frame. This
extends the 14-byte Ethernet header to a 16-byte header, which leads to the alignment of
the Ethernet payload, following the Ethernet header, on a 32-bit boundary.
This function can be enabled for transmit and receive independently with the corresponding
SHIFT16 bits in the ipaccTxConf register and ipaccRxConf register respectively.
When enabled, the valid frame data is arranged as shown in the table below.
Table 26-22. 64-Bit Interface Data Structure with SHIFT16 option enabled
63 56
55 48
47 40
39 32
31 24
23 16
15 8
7 0
Byte 5
Byte 4
Byte 3
Byte 2
Byte 1
Byte 0
Any value
Any value
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
1636
Freescale Semiconductor, Inc.