MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 224
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MCIMX286CVM4B
Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(70 pages)
2.MCIMX283DVM4B.pdf
(2 pages)
3.MCIMX283DVM4B.pdf
(2327 pages)
4.MCIMX283DVM4B.pdf
(20 pages)
Specifications of MCIMX286CVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
- MCIMX283DVM4B PDF datasheet
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Programmable Registers
5.4.59 Interrupt Collector Interrupt Register 49
This register provides a mechanism to specify the priority level for an interrupt source. It
also provides an enable and software interrupt for each one, as well as security designation.
HW_ICOLL_INTERRUPT49: 0x430
HW_ICOLL_INTERRUPT49_SET: 0x434
HW_ICOLL_INTERRUPT49_CLR: 0x438
HW_ICOLL_INTERRUPT49_TOG: 0x43C
224
Reset
PRIORITY
Bit
SOFTIRQ
W
RSRVD1
ENABLE
R
ENFIQ
Field
31 5
1 0
4
3
2
15
0
(HW_ICOLL_INTERRUPT49)
14
0
Always write zeroes to this bitfield.
Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through
the main IRQ FSM and priority logic.
0x0
0x1
Set this bit to one to force a software interrupt.
0x0
0x1
Enable the interrupt bit through the collector.
0x0
0x1
Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest).
0x0
0x1
0x2
0x3
13
0
DISABLE — Disable
ENABLE — Enable
NO_INTERRUPT — turn off the software interrupt request.
FORCE_INTERRUPT — force a software interrupt
DISABLE — Disable
ENABLE — Enable
LEVEL0 — level 0, lowest or weakest priority
LEVEL1 — level 1
LEVEL2 — level 2
LEVEL3 — level 3, highest or strongest priority
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_ICOLL_INTERRUPT48 field descriptions
12
0
11
0
RSRVD1[15:5]
10
0
0
9
0
8
Description
0
7
0
6
5
0
4
0
Freescale Semiconductor, Inc.
0
3
0
2
PRIORITY
0
1
0
0
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