MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 504

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

DMA Chain Example
semaphore. If the decompression software has not provided a buffer in a timely fashion,
then the DMA will stall. Without the decrement semaphore interlocking, then the DMA
will continue to output a stream of samples. In this mode, it is up to software to use the
interrupts to synchronize outputs so that underruns do not occur.
Note that each word of the three-word DMA command structure corresponds to a PIO
register of the DMA that is accessible on the APBX bus. Normally, the DMA copies the
next command structure onto these registers for processing at the start of each command
by following the value of the pointer previously loaded into the NEXTCMD_ADDR register.
To start DMA processing, for the first command, one must initialize the PIO registers of
the desired channel. First load the next command address register with a pointer to the first
command to be loaded. Then, write a one to the counting semaphore register. This causes
the DMA to schedule the targeted channel for DMA command structure load, as if it just
finished its previous command.
504
Figure 7-3. AHB-to-APBX Bridge DMA AUDIOOUT (DAC) Example Command Chain
512=0x200
1 PIO, IRQ, DecSema
HW_AUDIOOUT_CTRL0
chaining, DMA read
BUFFER ADDRESS
NEXTCMD_ADDR
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
(1.33 ms @
512-Byte
samples)
(64 PCM
48 kHz)
stereo
Block
Data
0x104E
(1.33 ms @
512-Byte
samples)
(64 PCM
48 kHz)
512=0x200
stereo
chaining, DMA read
Block
HW_AUDIOOUT_CTRL0
Data
BUFFER ADDRESS
NEXTCMD_ADDR
1 PIO, IRQ,
DecSema,
0x104E
512=0x200
HW_AUDIOOUT_CTRL0
BUFFER ADDRESS
NEXTCMD_ADDR
1 PIO,IRQ, DecSema,
chaining, DMA read
(1.33 ms @
512-Byte
(64 PCM
samples)
48 kHz)
stereo
Block
Data
0x104E
Pointer to DMA buffer
Pointer to next ccw
Freescale Semiconductor, Inc.