MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1253

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

15.4.8 GPMI Timing Register 0 (HW_GPMI_TIMING0)
The GPMI timing register 0 specifies the timing parameters that are used by the cycle state
machine to guarantee the various setup, hold and cycle times for the external media type.
Address:
Re-
Freescale Semiconductor, Inc.
set
Bit
W
ABORT_WAIT_
ABORT_WAIT_
R
TIMEOUT_IRQ
FOR_READY_
ATA_IRQRDY_
GPMI_MODE
DEV_RESET
DMA2ECC_
BURST_EN
POLARITY
REQUEST
CHANNEL
31
0
RSVD0
MODE
RSVD
Field
6 4
11
10
30
9
8
7
3
2
1
0
0
29
0
HW_GPMI_TIMING0
RSVD0
28
0
This is mainly for testing HWECC without involving the Nand device. Setting this bit will cause DMA write
data to redirected to HWECC module (instead of Nand Device) for encoding or decoding.
Always write zeros to this bit field.
This bit is set when a timeout occurs using the Device_Busy_Timeout value. Write 0 to clear.
When set to 1 each DMA request will generate a 4-transfer burst on the APB bus.
Request to abort the wait for ready command on the channel indicated by
ABORT_WAIT_FOR_READY_CHANNEL. Hardware clears this bit when the abort is done.
Abort a wait for ready command on selected channel. Set the ABORT_WAIT_REQUEST to kick of operation.
Nand Flash write protection control.
0x0
0x1
Always set this bit to 1.
Always write zeros to this bit field.
0= NAND mode.
This bit should be 0 only.
27
0
26
0
ENABLED — enable write protection for all Nand devices.
DISABLED — disable write protection for all Nand devices.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
HW_GPMI_CTRL1 field descriptions (continued)
24
0
23
0
8000_C000h base + 70h offset = 8000_C070h
22
0
ADDRESS_SETUP
21
0
20
0
19
0
18
0
17
0
16
1
15
0
Description
14
0
Chapter 15 General-Purpose Media Interface(GPMI)
13
DATA_HOLD
0
12
0
11
0
10
0
1
9
0
8
0
7
0
6
DATA_SETUP
0
5
0
4
3
0
0
2
1
1
1253
1
0