MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1327

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

17.8.4 SDIO Interrupts
The SSP supports SDIO interrupts. When the SSP is in SD/MMC mode and the SDIO_IRQ
bit in the HW_SSP_CTRL0 register is set, the SSP looks for interrupts on DATA1 during
the valid IRQ periods. The valid IRQ periods are defined in the SDIO specification. If the
card asserts an interrupt and SDIO_IRQ_EN is set, then the SSP sets the SDIO_IRQ status
bit and asserts a CPU IRQ. Other than detecting when card IRQs are valid, the SDIO IRQ
function operates independently from the rest of the SSP. After the CPU receives an IRQ,
it should monitor the SSP and DMA status to determine when it should send commands to
the SDIO card to handle the interrupt.
17.8.5 SD/MMC Mode Error Handling
There are several errors that can occur during the SD/MMC operation. These errors can be
caused by normal unexpected events, such as having a card removed or unusual events such
as a card failure. The detected error cases are listed below. Please note that in all the cases
below, a CPU IRQ is only asserted if DATA_CRC_IRQ_EN is set in HW_SSP_CTRL1
register.
Freescale Semiconductor, Inc.
• Data Receive CRC Error Detected by the SSP after a block receive. If this occurs,
• Data Transmit CRC Error Transmit CRC error token is received from the SD/MMC
the SSP will not indicate to DMA that the transfer is complete. It will set the
DATA_CRC_ERR status flag and assert a CPU IRQ. The ISR should reset the SSP
DMA channel and instruct the DMA to re-try the block read operation.
card on the DAT line after a block transmit. If this occurs, the SSP will not indicate to
DMA that the transfer is complete. It will set the DATA_CRC_ERR status flag and
assert a CPU IRQ. The ISR should reset the SSP DMA channel and instruct the DMA
to re-try the block write operation.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Chapter 17 Synchronous Serial Ports (SSP)
1327