MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 518

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
518
CH15_ERROR_
CH14_ERROR_
CH13_ERROR_
CH12_ERROR_
CH11_ERROR_
CH10_ERROR_
CH1_ERROR_
CH0_ERROR_
CH9_ERROR_
CH8_ERROR_
CH7_ERROR_
CH6_ERROR_
STATUS
STATUS
Field
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
17
16
15
14
13
12
11
10
9
8
7
6
0x0
0x1
Error status bit for APBX DMA Channel 1. Valid when corresponding Error IRQ is set.
1 - AHB bus error
0 - channel early termination.
0x0
0x1
Error status bit for APBX DMA Channel 0. Valid when corresponding Error IRQ is set.
1 - AHB bus error
0 - channel early termination.
0x0
0x1
Error interrupt status bit for APBX DMA Channel 15. This sticky bit is set by DMA hardware and reset by
software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM.
Error interrupt status bit for APBX DMA Channel 14. This sticky bit is set by DMA hardware and reset by
software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM.
Error interrupt status bit for APBX DMA Channel 13. This sticky bit is set by DMA hardware and reset by
software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM.
Error interrupt status bit for APBX DMA Channel 12. This sticky bit is set by DMA hardware and reset by
software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM.
Error interrupt status bit for APBX DMA Channel 11. This sticky bit is set by DMA hardware and reset by
software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM.
Error interrupt status bit for APBX DMA Channel 10. This sticky bit is set by DMA hardware and reset by
software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM.
Error interrupt status bit for APBX DMA Channel 9. This sticky bit is set by DMA hardware and reset by
software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM.
Error interrupt status bit for APBX DMA Channel 8. This sticky bit is set by DMA hardware and reset by
software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM.
Error interrupt status bit for APBX DMA Channel 7. This sticky bit is set by DMA hardware and reset by
software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM.
Error interrupt status bit for APBX DMA Channel 6. This sticky bit is set by DMA hardware and reset by
software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM.
TERMINATION — An early termination from the device causes error IRQ.
BUS_ERROR — An AHB bus error causes error IRQ.
TERMINATION — An early termination from the device causes error IRQ.
BUS_ERROR — An AHB bus error causes error IRQ.
TERMINATION — An early termination from the device causes error IRQ.
BUS_ERROR — An AHB bus error causes error IRQ.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_APBX_CTRL2 field descriptions (continued)
Description
Freescale Semiconductor, Inc.