MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1508

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MCIMX286CVM4B

Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r

Specifications of MCIMX286CVM4B

Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Rotary Decoder
A state machine following rotary decoder transition is provided to detect the direction of
rotation and the time at which to increment or decrement the 16-bit signed counter in
HW_TIMROT_ROTCOUNT. The updown counter can be treated as either a relative count
or an absolute count, depending on the state of the HW_TIMROT_ROTCTRL_RELATIVE
bit. When set to the relative mode, each read of the counter has the side effect of resetting
it. The edge detectors respond to both edges of each input to determine the self-timed
transition inputs to the state machine (see
Figure 23-8
Not all transitions are legal (see
directly from state 11 to 00 using normal inputs. In the cases where this occurs, the state
machine goes to an alternate set of states and follows the input sequence until a valid
sequence leading to state 00 is detected. No increment or decrement action is taken from
the alternate state sequence.
1508
Figure 23-7. Rotary Decoding Mode-Debouncing Rotary A and B Inputs
shows that each detected edge causes a transition in the decoder state machine.
Figure 23-8. Rotary Decoding Mode-Input Transitions
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
D
Input A
*Q
Input B
Q
D
*Q
ROTARY_A
ROTARY_B
Q
NEVER TICK
PWM[0]
PWM[1]
PWM[2]
PWM[5]
PWM[6]
PWM[3]
PWM[7]
PWM[4]
11
D
*Q
Q
Table
D
10
*Q
Q
D
*Q
23-2). For example, there is no legal way to transition
inc
Q
00
~oversamp_by_8
D
*Q
Q
Figure
~oversamp_by_8
10
D
*Q
Q
11
D
23-8).
*Q
Q
Flip-flops sample and
advance at a divided
32-kHz rate
01
dec
00
J
K
Q
Q*
01
Adebounce
Freescale Semiconductor, Inc.

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