MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 853

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

of the system as a whole. During a clock system context switch, intermediate clock
frequencies for the selected domains cannot be faster than the sub system or the I/O interface
which is designed to support.
It is expected that the sequence of events when a clock domain is tuned to a desired frequency
be managed by a software using a hardware status polling mechanism. Each parameter has
an associated enable bit so that all the divide parameters can be programmed in advance of
the parameters taking effect. A single register, hw_clkctrl_clkseq, contains all the enable
bits that cause the divide parameters to take effect. The enable bits can be set, the busy bits
can be polled for each parameter, and thus the enable/busy sequencing through software
control can manage the tuning of clock frequencies throughout the system.
10.5 Analog Clock Control
Analog clock control is performed indirectly through PIO accessable registers in the
CLKCTRL module. The analog circuits that are controlled through CLKCTRL PIO access
are the PLL and all instances of the phase fractional dividers, or PFDs.
10.6 CPU and EMI Clock Programming
A defined protocol is necessary for selecting clock frequencies and root sources for driving
the clk_p and clk_emi domains. These two clock structures are unique in that each implement
a separate divider, one referenced by xtal clock and the other referenced by a PLL/PFD
structure. The roots of these clocks must be programmed in order of the sources furthest
from the trunk first. Elements in the clock roots should subsequently be configured along
the root path up to the desired clock trunk. The programming sequence to go from a clock
that is referenced from the xtal clock to the PLL is outlined below. This is the case when
the device is in low power operation and there exists the need for higher clock rates to meet
the demands of a more compute-intensive application.
Freescale Semiconductor, Inc.
1. The crystal is the current source for the CPU or the EMI clock domain.
2. Enable the PLL.
3. Wait for PLL lock.
4. Program and enable the PFD with the desired configuration.
5. Clear the PFD clock gate to establish the desired reference clock frequency.
6. Program the CLKCTRL clock divider register (EMI or CPU) that uses the PLL/PFD
as its reference clock.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Chapter 10 Clock Generation and Control (CLKCTRL)
853