MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1226

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
Address:
Re-
14.8.167 DRAM Control Register 178 (HW_DRAM_CTL178)
This is a DRAM configuration register.
Address:
1226
set
Reset
Bit
W
R
Bit
31
W
0
TRP_AB
R
CKSRX
CKSRE
RSVD4
RSVD3
RSVD2
RSVD1
RSVD4
31 29
28 24
TCCD
23 20
19 16
15 12
Field
11 8
7 4
3 0
RSVD4
30
0
31
0
29
0
HW_DRAM_CTL178
HW_DRAM_CTL177
28
0
30
0
Always write zeroes to this field.
DRAM CAS-to-CAS parameter in cycles.
Defines the minimum delay between CAS commands, in cycles. This value is loaded into a counter when
a burst is issued and a new command may be issued when the counter reaches 0.
Always write zeroes to this field.
DRAM TRP All Bank parameter in cycles.
Defines the DRAM TRP time for all banks, in cycles.
Always write zeroes to this field.
Clock stable delay on self-refresh exit.
Sets the number of cycles to hold the clock stable before exiting self-refresh mode. The clock will run for a
minimum of cksrx cycles before CKE rises.
Always write zeroes to this field.
Clock hold delay on self-refresh entry.
Sets the number of cycles to hold the clock stable after entering self-refresh mode. The clock will run for a
minimum of cksre cycles after CKE falls.
27
0
TCCD
26
0
29
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
28
0
AXI5_BDW
23
0
HW_DRAM_CTL177 field descriptions
RSVD3
800E_0000h base + 2C8h offset = 800E_02C8h
800E_0000h base + 2C4h offset = 800E_02C4h
22
0
27
0
21
0
20
0
26
0
19
0
TRP_AB
18
25
0
0
17
0
16
24
0
0
15
0
Description
RSVD3
RSVD2
23
14
0
0
13
0
22
12
0
0
11
0
CKSRX
21
0
10
0
AXI4_CURRENT_BDW
0
9
20
0
0
8
Freescale Semiconductor, Inc.
0
7
19
RSVD1
0
0
6
0
5
18
0
0
4
3
0
17
0
CKSRE
0
2
0
1
16
0
0
0