MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1488

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
22.8.3 Real-Time Clock Milliseconds Counter
The millisecond count register provides a reliable elapsed time reference to the kernel with
millisecond resolution.
HW_RTC_MILLISECONDS: 0x020
HW_RTC_MILLISECONDS_SET: 0x024
HW_RTC_MILLISECONDS_CLR: 0x028
HW_RTC_MILLISECONDS_TOG: 0x02C
HW_RTC_MILLISECONDS provides access to the 32-bit millisecond counter. This counter
is not a shadow register, i.e., the contents of this register are not preserved over power-down
states. This counter increments once per millisecond based on a pulse from RTC analog
which is derived from the 24.0-MHz crystal clock. This 1-kHz source hence does not vary
as the APBX clock frequency is changed. The millisecond counter wraps at 4,294,967,294
milliseconds or 49.7 days.
EXAMPLE
milliseconds counter
counter.
1488
STALE_REGS
NEW_REGS
RSVD1
RSVD0
26 24
23 16
Field
15 8
7 0
(HW_RTC_MILLISECONDS)
HW_RTC_MILLISECONDS_WR(0);
Count = HW_RTC_MILLISECONDS_RD(); // read the current value of the milliseconds
Reserved, write only zeroes.
These read-only bits are set to one whenever the corresponding shadow register contents are older than
the analog side contents. These bits are set by reset and cleared by the copy controller. They are also set
by writing a one to the FORCE_UPDATE bit.
These read-only bits are set to one whenever the corresponding shadow register contents are newer than
the analog side contents. These bits are set by writing to the corresponding register and cleared by the copy
controller.
Reserved, write only zeroes.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_RTC_STAT field descriptions (continued)
// write an initial starting value to the
Description
Freescale Semiconductor, Inc.