MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1046

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
13.3.22 DCP Channel 1 Status Register (HW_DCP_CH1STAT)
The DCP Channel 1 Interrupt Status register contains the interrupt status bit and the tag of
the last completed operation from the command chain. If an error occurs during processing,
the ERROR bit is set and an interrupt is generated.
HW_DCP_CH1STAT: 0x160
HW_DCP_CH1STAT_SET: 0x164
HW_DCP_CH1STAT_CLR: 0x168
HW_DCP_CH1STAT_TOG: 0x16C
The interrupt status register is updated at the end of each work packet. If the interrupt bit
is set in the command packet's command field, an interrupt will be generated once the packet
has completed. In addition, the tag value from the command is stored in the TAG field so
that software can identify which command structure was the last to complete. If an error
occurs, the ERROR bit is set and processing of the command chain is halted.
Address:
1046
Reset
INCREMENT
Bit
W
R
RSVD1
Field
15 8
7 0
31
0
HW_DCP_CH1STAT
30
0
Reserved, always set to zero.
The value written to this field is added to the semaphore count in an atomic way such that simultaneous
software adds and DCP hardware substracts happening on the same clock are protected. This bit field reads
back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DCP
channel decrements the count on the same clock, then the count is incremented by a net one.The semaphore
may be cleared by writing 0xFF to the HW_DCP_CHnSEMA_CLR register.
29
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_DCP_CH1SEMA field descriptions (continued)
28
0
TAG
8002_8000h base + 160h offset = 8002_8160h
27
0
26
0
25
0
24
0
Description
23
0
22
0
21
0
ERROR_CODE
20
0
Freescale Semiconductor, Inc.
19
0
18
0
17
0
16
0