MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1946

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
Address:
1946
Reset
Reset
SEMAPHORE
INVERT_RTS
INVERT_CTS
DMAONERR
INVERT_TX
INVERT_RX
RXIFLSEL
Bit
Bit
RXDMAE
W
W
TXDMAE
R
R
RSVD2
22 20
RTS_
Field
31
30
29
28
27
26
25
24
23
31
15
0
0
HW_UARTAPP_CTRL2
30
14
0
0
Invert RTS signal. If this bit is set to 1, the RTS output is inverted before transmitted.
Invert CTS signal. If this bit is set to 1, the CTS input is inverted before sampled.
Invert TX signal. If this bit is set to 1, the TX output is inverted before transmitted.
Invert RX signal. If this bit is set to 1, the RX input is inverted before sampled.
If this bit is set to 1, RTS is deasserted when the semaphore threshold is less than 2.
DMA On Error. If this bit is set to 1, receive dma will terminate on error. (Cmd_end signal may not be asserted
when this occurs.)
Transmit DMA Enable. Data Register can be loaded with up to 4 bytes per write. TXFIFO must be enabled
in TXDMA mode.
Receive DMA Enable. Data Register can be contain up to 4 bytes per read. RXFIFO must be enabled in
RXDMA mode.
Reserved, do not modify, read as zero.
Receive Interrupt FIFO Level Select. The trigger points for the receive interrupt are as follows:
0x0
0x1
0x2
0x3
0x4
29
13
0
0
NOT_EMPTY — Trigger on FIFO containing at least 2 of 16 entries.
ONE_QUARTER — Trigger on FIFO full to at least 4 of 16 entries.
ONE_HALF — Trigger on FIFO full to at least 8 of 16 entries.
THREE_QUARTERS — Trigger on FIFO full to at least 12 of 16 entries.
SEVEN_EIGHTHS — Trigger on FIFO full to at least 14 of 16 entries.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
28
12
0
0
HW_UARTAPP_CTRL2 field descriptions
RTS
27
11
0
0
8006_A000h base + 20h offset = 8006_A020h
DTR
26
10
0
0
RXE
25
0
1
9
TXE
24
0
1
8
Description
LBE
23
0
0
7
USE_
LCR2
22
0
0
6
RXIFLSEL
21
1
5
0
RSVD4
20
0
4
0
Freescale Semiconductor, Inc.
19
0
0
3
18
0
0
2
TXIFLSEL
17
1
0
1
16
0
0
0