MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1608

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

10 100Mbps Ethernet ENET-MAC Core Features
Advanced Power Management features are available with Magic Packet detection and
programmable power down modes.
For industrial automation application, the IEEE 1588 standard is becoming the main
technology for precise time synchronization on Ethernet networks providing accurate clock
synchronization for distributed control nodes to overcome one of the drawbacks of Ethernet.
The programmable 10/100 Ethernet MAC with IEEE 1588 support integrates a standard
IEEE 802.3 Ethernet MAC with a time stamping module to support Ethernet applications
requiring precise timing references for incoming and outgoing frames to implement a
distributed time synchronization protocol such as the IEEE 1588.
26.3.2 10 100Mbps Ethernet ENET-MAC Core Features
26.3.2.1 Ethernet MAC Features
1608
• Implements the full 802.3 specification with preamble / SFD generation, frame padding
• Dynamically configurable to support 10 Mbps and 100 Mbps operation
• Supports full duplex and configurable half duplex operation
• Supports AMD Magic Packet detection with interrupt for node remote power
• Seamless interface to commercial Fast Ethernet PHY device through a 4-Bit Media
• Simple 64-Bit FIFO interface to user application
• CRC-32 checking at full speed with optional forwarding of the FCS field to client
• CRC-32 generation and append on transmit or forwarding of user application provided
• When operating in Full Duplex mode, implements automated Pause Frame (802.3
• When operating in full duplex mode, pause quanta used to form Pause frames,
• Pause frame generation additionally controllable by user application offering flexible
generation, CRC generation and checking
management
Independent Interface (MII) operating at 25MHz
FCS selectable on a per-frame basis
x31A) generation and termination providing flow control without user application
intervention
dynamically programmable
traffic flow control
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.