MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2075

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Chapter 33 LCD Interface (LCDIF)
VSYNC_PERIOD_UNIT bit fields. The VERTICAL_WAIT_CNT is by default given the
same unit as the VSYNC_PERIOD. The CLK_DIS_LCDIFn is controlled using the
HW_CLKCTRL_PIX, HW_CLKCTRL_FRAC, and HW_CLKCTRL_CLKSEQ registers
in the CLCKTRL block.
In DOTCLK mode, HW_LCDIF_CTRL_BYPASS_COUNT bit must be set to 1. To end
the current transfer, the software should make the DOTCLK_MODE bit 0, so that all data
that is currently in the LCDIF LFIFO and TXFIFO is transmitted. Once that transfer is
complete, the block will automatically clear the RUN bit and issue the cur_frame_done
interrupt.
33.2.8.1 Code Example
The following code shows an example for programming a 320x240 display. Note that setting
up the display must be done through the MPU mode or through SPI.
// Note: Common initialization steps in
Initializing the LCDIF
must also be
// executed along with the following code
BF_CS1 (LCDIF_CTRL, DOTCLK_MODE, 1);
BF_CS1 (LCDIF_CTRL, BYPASS_COUNT, 1); //Always for DOTCLK mode
BF_CS1 (LCDIF_VDCTRL0, VSYNC_OEB, 0); //Vsync is always an output in the DOTCLK mode
BF_CS4 (LCDIF_VDCTRL0, VSYNC_POL, 0, HSYNC_POL, 0, DOTCLK_POL, 0, ENABLE_POL, 0);
BF_CS1 (LCDIF_VDCTRL0, ENABLE_PRESENT, 1);
BF_CS2 (LCDIF_VDCTRL0, VSYNC_PERIOD_UNIT, 1, VSYNC_PULSE_WIDTH_UNIT, 1);
BF_CS1 (LCDIF_VDCTRL0, VSYNC_PULSE_WIDTH, 2);
BF_CS1 (LCDIF_VDCTRL1, VSYNC_PERIOD, 280);
BF_CS2 (LCDIF_VDCTRL2, HSYNC_PULSE_WIDTH, 10, HSYNC_PERIOD, 360); //Assuming LCD_DATABUS_WIDTH
//
is 24bit
BF_CS2 (LCDIF_VDCTRL3, VSYNC_ONLY, 0);
BF_CS2 (LCDIF_VDCTRL3, HORIZONTAL_WAIT_CNT, 20, VERTICAL_WAIT_CNT, 20);
BF_CS1 (LCDIF_VDCTRL4, DOTCLK_H_VALID_DATA_CNT, 320);//Note that DOTCLK_V_VALID_DATA_CNT is
//implicitly assumed to be
HW_LCDIF_TRANSFER_COUNT_V_COUNT
BF_CS1 (LCDIF_VDCTRL4, SYNC_SIGNALS_ON, 1);
BF_CS1 (LCDIF_CTRL, RUN, 1);
To stop the transfer completely, the ideal way is to make DOTCLK_MODE = 0. In that
case, the block will transmit whatever it had in its FIFO, turn off the RUN bit and toggle
the dma_end_cmd signal indicating to the DMA that it is done with the transfer.
33.2.9 ITU-R BT.656 Digital Video Interface (DVI)
ITU-R BT.656 Digital Video Interface shown below transmits 4:2:2 YCbCr digital
component video to a digital video encoder that can translate it into 525/60 or 625/50 analog
TV signal. Unique timing codes (timing reference signals) are embedded within the video
stream to indicate the different timing events that would have been otherwise indicated by
VSYNC, HSYNC and BLANK signals. The hardware supports 8-bit data transfers; the pins
are shared with the lower 8 bits of LCD data bus. The LCD_RS pin is shared with the clock
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.
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