MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1529

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Chapter 24
Debug UART (DUART)
24.1 Debug UART Overview
The Debug UART performs:
The CPU reads and writes data and control/status information through the APBX interface.
The transmit and receive paths are buffered with internal FIFO memories, enabling up to
32 bytes to be stored independently in both transmit and receive modes.
The Debug UART includes a programmable baud rate generator that creates a transmit and
receive internal clock from the 24-MHz UART internal reference clock input UARTCLK.
XCLK is not tied to the UARTCLK in the i.MX28.
It offers similar functionality to the industry-standard 16C550 UART device and supports
baud rates of up to 115 Kb/s.
Debug UART operation and baud rate values are controlled by the line control register
(HW_UARTDBGLCR_H, HW_UARTDBGIBRD, and HW_UARTDBGFBRD).
The Debug UART can generate a single combined interrupt, so output is asserted if any
individual interrupt is asserted and unmasked. Interrupt sources include the receive (including
timeout), transmit, modem status, and error conditions.
If a framing, parity, or break error occurs during reception, the appropriate error bit is set,
and is stored in the FIFO. If an overrun condition occurs, the overrun register bit is set
immediately, and FIFO data is prevented from being overwritten. You can program the
FIFOs to be one-byte deep, providing a conventional double-buffered UART interface.
The modem status input signal Clear To Send (CTS) and output modem control line Request
To Send (RTS) are supported. A programmable hardware flow control feature uses the
nUARTCTS input and the nUARTRTS output to automatically control the serial data flow.
Freescale Semiconductor, Inc.
• Serial-to-parallel conversion on data received from a peripheral device
• Parallel-to-serial conversion on data transmitted to the peripheral device
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Figure 24-1
shows a block diagram of the Debug UART. The
1529