MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1113

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Address:
14.8.3 DRAM Control Register 02 (HW_DRAM_CTL02)
This is a DRAM configuration register.
Address:
Re-
Freescale Semiconductor, Inc.
Reset
Reset
set
Bit
MON_DBG_STB
W
MON_DISABLE
R
USER_DEF_
Bit
Bit
W
W
31
SLVERR
0
R
R
REG_1
31 9
Field
7 4
3 0
30
8
0
31
15
0
0
29
0
HW_DRAM_CTL01
HW_DRAM_CTL02
28
0
30
14
0
0
User-defined output register 1.
Holds user-defined values that will be available as output signals param_user_def_reg_X (where X ranges
from 0 to 7)
Setting this bit to a logic 1 will initiate sampling the state of each AXI interface monitor. The diagnostic
information available in the debug registers is valid only after this bit is set to a logic one. To take a subsequent
snapshot of the state of each AXI monitor, set this bit low, and then high again.
Setting this bit will cause all AXI transactions to be processed with a slave error when the respective monitor
is enabled.
Setting this bit will disable the AXI monitors. None of the EMI AXI error conditions will be checked and all
AXI traffic will proceed.
27
USER_DEF_REG_1[15:9]
0
26
0
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
28
12
0
0
23
0
800E_0000h base + 4h offset = 800E_0004h
HW_DRAM_CTL01 field descriptions
800E_0000h base + 8h offset = 800E_0008h
22
0
27
11
0
0
21
0
20
26
10
0
0
0
19
0
USER_DEF_REG_1[31:16]
18
25
USER_DEF_REG_2
0
0
0
9
17
0
24
16
0
0
0
8
15
0
Description
23
14
0
0
7
0
13
0
22
SLVERR
0
0
12
6
0
Chapter 14 External Memory Interface (EMI)
11
0
21
0
5
0
10
0
0
9
20
0
4
0
0
8
0
7
19
0
0
3
0
6
MON_DISABLE
0
5
18
0
0
2
0
4
3
0
17
0
0
1
0
2
0
1
1113
16
0
0
0
0
0