MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1135

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

14.8.30 DRAM Control Register 32 (HW_DRAM_CTL32)
This is a DRAM configuration register.
Address:
Freescale Semiconductor, Inc.
Reset
Reset
DRIVE_DQ_DQS
EIGHT_BANK_
DQS_N_EN
Bit
Bit
W
W
R
R
RSVD3
RSVD2
RSVD1
MODE
23 17
Field
15 9
7 1
16
8
0
31
15
0
0
HW_DRAM_CTL32
30
14
0
0
Always write zeroes to this field.
Number of banks on the DRAM(s).
Indicates that the memory devices have eight banks.
'b0 = Memory devices have 4 banks.
'b1 = Memory devices have 8 banks.
Always write zeroes to this field.
Sets DQ/DQS output enable behavior when controller is idle.
Selects if the DQ output enables and DQS output enables will be driven active when the EMI is in an idle
state.
'b0 = Leave the output enables in their current state when idle.
'b1 = Drive the idle_drive_enable signal high when idle.
Always write zeroes to this field.
Set DQS pin as single-ended or differential.
Enables differential data strobe signals from the DRAM. This parameter is only relevant for the DDR PHY.
'b0 = Single-ended DQS signal from the DRAM.
'b1 = Differential DQS signal from the DRAM.
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_DRAM_CTL31 field descriptions (continued)
RSVD2
28
12
0
0
800E_0000h base + 80h offset = 800E_0080h
27
11
0
0
26
10
0
0
25
0
0
9
OBSOLETE
24
0
0
8
Description
23
0
0
7
22
0
0
6
Chapter 14 External Memory Interface (EMI)
21
0
5
0
RSVD1
20
0
4
0
19
0
0
3
18
0
0
2
17
0
0
1
1135
16
0
0
0