MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1569

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

f
25.4.10.2 Overload Frames
FlexCAN does transmit overload frames due to detection of the following conditions on
CAN bus:
25.4.10.3 Time Stamp
The value of the Free Running Timer is sampled at the beginning of the Identifier field on
the CAN bus, and is stored at the end of move-in in the TIME STAMP field, providing
network behavior with respect to time.
The Free Running Timer can be reset upon a specific frame reception, enabling network
time synchronization.
25.4.10.4 Protocol Timing
The FlexCAN only supports the crystal oscillator clock as the CPI clock.
The crystal oscillator clock should be selected whenever a tight tolerance (up to 0.1%) is
required in the CAN bus timing. The crystal oscillator clock has better jitter performance
than PLL generated clocks.
The FlexCAN module supports a variety of means to setup bit timing parameters that are
required by the CAN protocol. The Control Register has various fields used to control bit
timing parameters: PRESDIV, PROPSEG, PSEG1, PSEG2 and RJW.
The PRESDIV field controls a prescaler that generates the Serial Clock (Sclock), whose
period defines the 'time quantum' used to compose the CAN waveform. A time quantum is
the atomic unit of time handled by the CAN engine.
A bit time is subdivided into three segments
3.
Freescale Semiconductor, Inc.
Tq
For further explanation of the underlying concepts please refer to ISO/DIS 11519 1, Section 10.3. Reference also the Bosch
CAN 2.0A/B protocol specification dated September 1991 for bit timing.
• Detection of a dominant bit in the first/second bit of Intermission
• Detection of a dominant bit at the seventh bit (last) of End of Frame field (Rx frames)
• Detection of a dominant bit at the eighth bit (last) of Error Frame Delimiter or Overload
=
Frame Delimiter
(PrescalerValue)
f
CANCLK
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
3
(reference
Chapter 25 Controller Area Network (FlexCAN)
Figure 25-2
and
Table
25-6):
1569