MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1581

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
Reset
RWRN_MSK
TWRN_MSK
BOFF_MSK
BOFF_REC
ERR_MSK
CLK_SRC
Bit
PRESDIV
W
R
PSEG1
PSEG2
31 24
23 22
21 19
18 16
RSVD
TSYN
LBUF
Field
RJW
SMP
LOM
LPB
9 8
15
14
13
12
11
10
7
6
5
4
3
15
0
ERR_
MSK
14
0
This 8-bit field defines the ratio between the CPI clock frequency and the serial clock (SCLK) frequency.
This 2-bit field defines the maximum number of time quanta that a bit time can be changed by one RJW
re-synchronization.
This 3-bit field defines the length of phase buffer segment 1 in the bit time.
This 3-bit field defines the length of phase buffer segment 2 in the bit time.
This bit provides a mask for the bus-off interrupt.
This bit provides a mask for the error interrupt.
This bit selects the clock source to the CAN Protocol Interface (CPI) to be either the peripheral clock (driven
by the PLL) or the crystal oscillator clock.
In i.MX28, the clock source is just from the crystal oscillator clock. Setting this bit has no effects.
This bit configures CAN to operate in Loop-Back Mode.
This bit provides a mask for the TxWarning Interrupt associated with the TWRN_INT flag in the Error and
Status Register.
This bit provides amask for the RxWarning Interrupt associated with the RWRN_INT flag in the Error and
Status Register.
Reserved.
This bit defines the sampling mode of CAN bits at the Rx input.
This bit defines how CAN recovers from the bus-off state.
This bit enables a mechanism that resets the free-running timer each time a message is received in Message
Buffer 0.
This bit defines the ordering mechanism for Message Buffer transmission.
This bit configures CAN to operate in Listen Only Mode.
CLK_
SRC
13
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
LPB
12
0
HW_CAN_CTRL field descriptions
11
0
10
0
0
9
RSVD
0
8
Description
SMP
0
7
Chapter 25 Controller Area Network (FlexCAN)
0
6
5
0
LBUF
4
0
LOM
0
3
0
2
PROP_SEG
0
1
1581
0
0