MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 890

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
890
Reset
BYPASS_SSP3
BYPASS_SSP2
BYPASS_SSP1
BYPASS_SSP0
BYPASS_GPMI
BYPASS_CPU
BYPASS_DIS_
BYPASS_ETM
BYPASS_EMI
Bit
W
RSRVD0
RSRVD1
RSRVD2
R
31 19
17 15
LCDIF
Field
13 9
R S R V D 1
[15:15]
18
14
8
7
6
5
4
3
2
15
1
14
0
Always set to zero (0).
CPU bypsss select. 1 = Select ref_xtal path to generate the CPU clock domain. 0 = Select ref_cpu path to
generate the CPU clock domain. PLL0 and 9-phase fractional divider must already be configured when
changing from bypass mode.
Always set to zero (0).
LCDIF bypsss select. 1 = Select ref_xtal path to generate the LCDIF clock domain. 0 = Select ref_pix path
to generate the LCDIF clock domain. PLL0 and 9-phase fractional divider must already be configured when
changing from bypass mode.
0x1
0x0
Always set to zero (0).
ETM bypass select. 1 = Select ref_xtal path to generate the ETM clock domain. 0 = Select ref_cpu path to
generate the ETM clock domain. PLL0 and 9-phase fractional divider must already be configured when this
bit is cleared.
EMI bypass select. 1 = Select ref_xtal path to generate the EMI clock domain. 0 = Select ref_emi path to
generate the EMI clock domain. PLL0 and 9-phase fractional divider must already be configured when this
bit is cleared.
SSP3 bypass select. 1 = Select ref_xtal path to generate the SSP3 clock domain. 0 = Select ref_io1 path
to generate the SSP3 clock domain. PLL0 and 9-phase fractional divider must already be configured when
this bit is cleared.
SSP2 bypass select. 1 = Select ref_xtal path to generate the SSP2 clock domain. 0 = Select ref_io1 path
to generate the SSP2 clock domain. PLL0 and 9-phase fractional divider must already be configured when
this bit is cleared.
SSP1 bypass select. 1 = Select ref_xtal path to generate the SSP1 clock domain. 0 = Select ref_io0 path
to generate the SSP1 clock domain. PLL0 and 9-phase fractional divider must already be configured when
this bit is cleared.
SSP0 bypass select. 1 = Select ref_xtal path to generate the SSP0 clock domain. 0 = Select ref_io0 path
to generate the SSP0 clock domain. PLL0 and 9-phase fractional divider must already be configured when
this bit is cleared.
GPMI bypass select. 1 = Select ref_xtal path to generate the GPMI clock domain. 0 = Select ref_gpmi path
to generate the GPMI clock domain. PLL0 and 9-phase fractional divider must already be configured when
this bit is cleared.
13
0
BYPASS — select xtal source, bypass mode
PFD — select PFD, ref_pix
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
12
HW_CLKCTRL_CLKSEQ field descriptions
0
RSRVD2
11
0
10
0
1
9
1
8
Description
1
7
1
6
5
1
4
1
Freescale Semiconductor, Inc.
1
3
1
2
1
1
1
0