MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1560

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Functional Description
When LBUF is asserted, the LPRIO_EN bit has no effect and the lowest number buffer is
transmitted first. When LBUF and LPRIO_EN are both negated, the MB with the lowest
ID is transmitted first. But, if LBUF is negated and LPRIO_EN is asserted, the PRIO bits
augment the ID used during the arbitration process. With this extended ID concept, arbitration
is performed based on the full 32-bit ID and the PRIO bits define which MB should be
transmitted first, therefore MBs with PRIO = 000 have higher priority. If two or more MBs
have the same priority, the regular ID will determine the priority of transmission. If two or
more MBs have the same priority (3 extra bits) and the same regular ID, the lowest MB
will be transmitted first.
Once the highest priority MB is selected, it is transferred to a temporary storage space called
Serial Message Buffer (SMB), which has the same structure as a normal MB but is not user
accessible. This operation is called move-out and after it is done, write access to the
corresponding MB is blocked (if the AEN bit in MCR is asserted). The write access is
released in the following events:
At the first opportunity window on the CAN bus, the message on the SMB is transmitted
according to the CAN protocol rules. FlexCAN transmits up to eight data bytes, even if the
DLC (Data Length Code) value is bigger.
25.4.4 Receive Process
To be able to receive CAN frames into the mailbox MBs, the ARM must prepare one or
more Message Buffers for reception by executing the following steps:
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• During Intermission, if the winner MB defined in a previous arbitration was deactivated,
• When MBM is in Idle or Bus Off state and the ARM writes to the C/S word of any MB
• Upon leaving Freeze Mode
• After the MB is transmitted
• FlexCAN enters in HALT or BUS OFF
• FlexCAN loses the bus arbitration or there is an error during the transmission
• If the MB has a pending transmission, write an ABORT code ('1001') to the Code field
or if there was no MB to transmit, but the ARM wrote to the C/S word of any MB after
the previous arbitration finished
of the Control and Status word to request an abortion of the transmission, then read
back the Code field and the IFLAG register to check if the transmission was aborted
(see
Transmission Abort
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Mechanism). If backwards compatibility is desired (AEN in
Freescale Semiconductor, Inc.