MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2005

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
Field
OCC
FPR
6
5
The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was
written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not
change until the port is suspended and that there may be a delay in suspending a port if there is a transaction
currently in progress on the USB.
The host controller will unconditionally set this bit to 0 when software sets the Force Port Resume bit to 0.
The host controller ignores a write of 0 to this bit.
If host software sets this bit to a 1 when the port is not enabled (i.e., Port enabled bit is a 0) the results are
undefined.
This field is 0 if Port Power (PP) is 0 in host mode.
In Device Mode: (Read-Only)
1 = Port in suspend state.
0 = Port not in suspend state.
Default=0.
In device mode, this bit is a Read-Only status bit.
Force Port Resume.
0 = No resume (K-state) detected/driven on port.
1 = Resume detected/driven on port.
Default = 0.
In Host Mode:
Software sets this bit to 1 to drive resume signaling. The Host Controller sets this bit to 1 if a J-to-K transition
is detected while the port is in the Suspend state. When this bit transitions to a 1 because a J-to-K transition
is detected, the Port Change Detect bit in the USBSTS register is also set to 1. This bit will automatically
change to 0 after the resume sequence is complete. This behavior is different from EHCI where the host
controller driver is required to set this bit to a 0 after the resume duration is timed in the driver.
Note that when the Host controller owns the port, the resume sequence follows the defined sequence
documented in the USB Specification Revision 2.0.
The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a 1. This bit will remain
a 1 until the port has switched to the high-speed idle. Writing a 0 has no effect because the port controller
will time the resume operation and clear the bit when the port control state switches to HS or FS idle.
This field is 0 if Port Power (PP) is 0 in host mode.
This bit is not-EHCI compatible.
In Device Mode:
After the device has been in Suspend State for 5 ms or more, software must set this bit to 1 to drive resume
signaling before clearing. The Device Controller will set this bit to 1 if a J-to-K transition is detected while
the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. Also,
when this bit transitions to a 1 because a J-to-K transition has been detected, the Port Change Detect bit in
the USBSTS register is also set to 1.
Over-Current Change.
0 = Default.
1 = This bit gets set to 1 when there is a change to Over-Current Active. Software clears this bit by writing
a 1 to this bit position.
HW_USBCTRL_PORTSC1 field descriptions (continued)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Chapter 31 USB High-Speed On-the-Go Host Device Controller
Description
2005