MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1318

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MCIMX286CVM4B

Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r

Specifications of MCIMX286CVM4B

Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Motorola SPI Mode
17.5.5 Motorola SPI Format with Polarity=1, Phase=0
Single and continuous transmission signal sequences for Motorola SPI format with
POLARITY=1 and PHASE=0 are shown in
Figure 17-5. Motorola SPI Frame Format (Single Transfer) with POLARITY=1 and PHASE=0
In this configuration, during idle periods:
If the SSP is enabled and there is valid data within the FIFO, the start of transmission is
signified by the SSn master signal being driven low, which causes slave data to be
immediately transferred onto the MISO line of the master, and enabling the master MOSI
output pad.
1318
Figure 17-6. Motorola SPI Frame Format (Continuous Transfer) with POLARITY=1 and
• The SSP_SCK signal is forced high.
• SSn is forced high.
• The Transmit data line MOSI is arbitrarily forced low.
• When the SSP is configured as a master, the SSP_SCK pad is an output.
• When the SSP is configured as a slave, the SSP_SCK is an input.
In
Figure
SSP_SCK
MOSI/MISO
SSP_SCK
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
MISO
MOSI
SSn
SSn
17-5, Q is an undefined signal.
LSB
MSB
MSB
MSB
PHASE=0
Note
Figure 17-5
4 to 16 bits
4 to 16 bits
and
LSB
Figure
LSB
LSB
17-6.
MSB
Freescale Semiconductor, Inc.
Q

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