MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1981

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
Reset
Bit
W
R
RSVD3
ATDTW
RSVD2
SUTW
31 24
23 16
ASPE
Field
FS2
ITC
15
14
13
12
11
FS2
15
0
14
0
Reserved.
Interrupt Threshold Control.
Default 0x08.
The system software uses this field to set the maximum rate at which the host/device controller will issue
interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are:
0x0
0x1
0x2
0x4
0x8
0x10
0x20
0x40
Bit 2 of Frame List Size field. See definition of bit FS0 for the complete definition.
Add dTD TripWire (device mode only).
This bit is used as a semaphore to ensure the proper addition of a new dTD to an active (primed) endpoint's
linked list. This bit is set and cleared by software. This bit shall also be cleared by hardware when is state
machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized.
Setup TripWire (device mode only).
This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by
the DCD without being corrupted. If the setup lockout mode is off (See USBMODE) then there exists a
hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a
previous setup packet. This bit is set and cleared by software and will be cleared by hardware when a hazard
exists.
Reserved.
Asynchronous Schedule Park Mode Enable (OPTIONAL).
When S/W changes the USBMODE.CM to Host(11), this bit defaults to 0x1. Software uses this bit to enable
or disable Park mode.
When this bit is 1, Park mode is enabled.
When this bit is a 0, Park mode is disabled.
This field is set to 1 in host mode; 0 in device mode.
13
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
IMM — Immediate (no threshold).
1_MICROFRAME — 1_MICROFRAME.
2_MICROFRAME — 2_MICROFRAME.
4_MICROFRAME — 4_MICROFRAME.
8_MICROFRAME — 8_MICROFRAME.
16_MICROFRAME — 16_MICROFRAME.
32_MICROFRAME — 32_MICROFRAME.
64_MICROFRAME — 64_MICROFRAME.
RSVD2
HW_USBCTRL_USBCMD field descriptions
12
0
ASPE
11
0
RSVD1
10
0
0
9
ASP
Chapter 31 USB High-Speed On-the-Go Host Device Controller
0
8
Description
LR
0
7
IAA
0
6
ASE
5
0
PSE
4
0
FS1
0
3
FS0
0
2
RST
0
1
RS
1981
0
0