MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1558

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Functional Description
Specifies an ID to be used as acceptance criteria for the FIFO. In both standard and extended
frame formats, all eight bits of the field are compared to the eight most significant bits of
the received ID.
25.4 Functional Description
25.4.1 Overview
The FlexCAN module is a CAN protocol engine with a very flexible mailbox system for
transmitting and receiving CAN frames. The mailbox system is composed by a set of 64
Message Buffers (MB) that store configuration and control data, time stamp, message ID
and data (see
Message Buffer
Structure). The memory corresponding to the first 8 MBs can
be configured to support a FIFO reception scheme with a powerful ID filtering mechanism,
capable of checking incoming frames against a table of IDs (up to 8 extended IDs or 16
standard IDs or 32 8-bit ID slices), each one with its own individual mask register.
Simultaneous reception through FIFO and mailbox is supported. For mailbox reception, a
matching algorithm makes it possible to store received frames only into MBs that have the
same ID programmed on its ID field. A masking scheme makes it possible to match the ID
programmed on the MB with a range of IDs on received CAN frames. For transmission, an
arbitration algorithm decides the prioritization of MBs to be transmitted based on the message
ID (optionally augmented by three local priority bits) or the MB ordering.
Before proceeding with the functional description, an important concept must be explained.
A Message Buffer is said to be active at a given time if it can participate in the matching
and arbitration algorithms that are happening at that time. An Rx MB with a 0000 code is
inactive (refer to
Table
25-2). Similarly, a Tx MB with a 1000 or 1001 code is also inactive
(refer to
Table
25-3). An MB not programmed with 0000, 1000 or 1001 is temporarily
deactivated (does not participate in the current arbitration or matching run) when the ARM
writes to the C/S field of that MB (see
Message Buffer
Deactivation).
The FlexCAN also provide a glitch filter which can filter the noises on CAN bus when the
FlexCAN is in the STOP mode. The glitch filter width is configurable by the register
HW_CAN_GFWR.
25.4.2 Transmit Process
In order to transmit a CAN frame, the ARM must prepare a Message Buffer for transmission
by executing the following procedure:
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
1558
Freescale Semiconductor, Inc.