MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1760

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
1760
MASTER_LOSS_
BUS_FREE_IRQ
SLAVE_IRQ_EN
DATA_ENGINE_
EARLY_TERM_
SLAVE_STOP_
XFER_TERM_
NO_SLAVE_
CMPLT_IRQ
OVERSIZE_
ACK_IRQ
IRQ_EN
IRQ_EN
IRQ_EN
IRQ_EN
Field
12
11
10
9
8
7
6
5
0x0
0x1
Set this bit to one to enable interrupt requests to be routed to the interrupt collector. Set to zero to disable
interrupts from the I2C controller.
0x0
0x1
Set this bit to one to enable interrupt requests to be routed to the interrupt collector. Set to zero to disable
interrupts from the I2C controller.
0x0
0x1
Set this bit to one to enable interrupt requests to be routed to the interrupt collector. Set to zero to disable
interrupts from the I2C controller.
0x0
0x1
Set this bit to one to enable interrupt requests to be routed to the interrupt collector. Set to zero to disable
interrupts from the I2C controller.
0x0
0x1
Set this bit to one to enable interrupt requests to be routed to the interrupt collector. Set to zero to disable
interrupts from the I2C controller. The corresponding HW_I2C_CTRL1_SLAVE_IRQ interrupt bit is set by
the slave search engine to indicate that it has stopped searching due to an address match or error.
0x0
0x1
This bit is set to indicate that an interrupt is requested by the I2C controller because the bus has become
free. This bit is cleared by software by writing a one to its SCT clear address. This interrupt indicates that
the I2C bus, which was busy, has just become free.
0x0
0x1
This bit is set to indicate that an interrupt is requested by the I2C controller because the data engine transfer
has completed. This bit is cleared by software by writing a one to its SCT clear address. This interrupt
indicates that the data engine has completed a DMA transfer in either master or slave mode. This notification
is useful for pio mode master write (transmit) or slave read (transmit) operations, i.e., data engine transmit
operations. PIO receive operations are not supported.
0x0
0x1
This bit is set to indicate that an interrupt is requested by the I2C controller because the slave addressed
by a master transfer did not respond with an acknowledge. This bit is cleared by software by writing a one
to its SCT clear address.
0x0
0x1
DISABLED — No Interrupt Request Pending.
ENABLED — Interrupt Request Pending.
DISABLED — No Interrupt Request Pending.
ENABLED — Interrupt Request Pending.
DISABLED — No Interrupt Request Pending.
ENABLED — Interrupt Request Pending.
DISABLED — No Interrupt Request Pending.
ENABLED — Interrupt Request Pending.
DISABLED — No Interrupt Request Pending.
ENABLED — Interrupt Request Pending.
DISABLED — No Interrupt Request Pending.
ENABLED — Interrupt Request Pending.
NO_REQUEST — No Interrupt Request Pending.
REQUEST — Interrupt Request Pending.
NO_REQUEST — No Interrupt Request Pending.
REQUEST — Interrupt Request Pending.
NO_REQUEST — No Interrupt Request Pending.
REQUEST — Interrupt Request Pending.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_I2C_CTRL1 field descriptions (continued)
Description
Freescale Semiconductor, Inc.